Search

Mohammed A. Bashar

Examiner (ID: 13174, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
746
Issued Applications
652
Pending Applications
90
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17302762 [patent_doc_number] => 20210398601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => DIRECT TESTING OF IN-PACKAGE MEMORY [patent_app_type] => utility [patent_app_number] => 17/349612 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/349612
Direct testing of in-package memory Jun 15, 2021 Issued
Array ( [id] => 18053910 [patent_doc_number] => 11527301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Method for reading and writing and memory device [patent_app_type] => utility [patent_app_number] => 17/342492 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 10228 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/342492
Method for reading and writing and memory device Jun 7, 2021 Issued
Array ( [id] => 17115282 [patent_doc_number] => 20210295879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/340681 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340681
Flexible memory system with a controller and a stack of memory Jun 6, 2021 Issued
Array ( [id] => 17757990 [patent_doc_number] => 11398288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Storage medium-assisted system interface training scheme [patent_app_type] => utility [patent_app_number] => 17/326414 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 14890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326414
Storage medium-assisted system interface training scheme May 20, 2021 Issued
Array ( [id] => 17070415 [patent_doc_number] => 20210272632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MEMORY DEVICE USING COMB-LIKE ROUTING STRUCTURE FOR REDUCED METAL LINE LOADING [patent_app_type] => utility [patent_app_number] => 17/317215 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317215
Memory device using comb-like routing structure for reduced metal line loading May 10, 2021 Issued
Array ( [id] => 18371653 [patent_doc_number] => 11651834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Memory duty-cycle skew management [patent_app_type] => utility [patent_app_number] => 17/316765 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316765
Memory duty-cycle skew management May 10, 2021 Issued
Array ( [id] => 17551343 [patent_doc_number] => 20220122685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/313236 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313236
Semiconductor memory devices and memory systems including the same May 5, 2021 Issued
Array ( [id] => 17963409 [patent_doc_number] => 20220343990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => OPTIMIZING MEMORY ACCESS OPERATION PARAMETERS [patent_app_type] => utility [patent_app_number] => 17/302215 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17302215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/302215
Optimizing memory access operation parameters Apr 26, 2021 Issued
Array ( [id] => 17424092 [patent_doc_number] => 11257553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Flash memory cell and associated high voltage row decoder [patent_app_type] => utility [patent_app_number] => 17/239397 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5859 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239397
Flash memory cell and associated high voltage row decoder Apr 22, 2021 Issued
Array ( [id] => 17963408 [patent_doc_number] => 20220343989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => AUTO-POWER ON MODE FOR BIASED TESTING OF A POWER MANAGEMENT INTEGRATED CIRCUIT (PMIC) [patent_app_type] => utility [patent_app_number] => 17/237875 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237875 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237875
Auto-power on mode for biased testing of a power management integrated circuit (PMIC) Apr 21, 2021 Issued
Array ( [id] => 18013541 [patent_doc_number] => 11505825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Methods of synthesizing DNA [patent_app_type] => utility [patent_app_number] => 17/233186 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 94 [patent_figures_cnt] => 123 [patent_no_of_words] => 62281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233186
Methods of synthesizing DNA Apr 15, 2021 Issued
Array ( [id] => 17529713 [patent_doc_number] => 11302411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks [patent_app_type] => utility [patent_app_number] => 17/219308 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219308
Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks Mar 30, 2021 Issued
Array ( [id] => 17447918 [patent_doc_number] => 20220068423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => Level Dependent Error Correction Code Protection in Multi-Level Non-Volatile Memory [patent_app_type] => utility [patent_app_number] => 17/213486 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213486
Level dependent error correction code protection in multi-level non-volatile memory Mar 25, 2021 Issued
Array ( [id] => 17757993 [patent_doc_number] => 11398291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device [patent_app_type] => utility [patent_app_number] => 17/213675 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 11855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213675
Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device Mar 25, 2021 Issued
Array ( [id] => 16965984 [patent_doc_number] => 20210217483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => Method, Apparatus and Electronic Device for Texting Memory, and Computer-Readable Storage Medium [patent_app_type] => utility [patent_app_number] => 17/213717 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213717
Method, apparatus and electronic device for texting memory, and computer-readable storage medium Mar 25, 2021 Issued
Array ( [id] => 19781313 [patent_doc_number] => 12230351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => On-chip power regulation circuitry and regulation method thereof [patent_app_type] => utility [patent_app_number] => 17/912766 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5725 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17912766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/912766
On-chip power regulation circuitry and regulation method thereof Mar 24, 2021 Issued
Array ( [id] => 17326279 [patent_doc_number] => 11217304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Memory operation method and circuit [patent_app_type] => utility [patent_app_number] => 17/207114 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207114
Memory operation method and circuit Mar 18, 2021 Issued
Array ( [id] => 17389106 [patent_doc_number] => 20220036958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DEFECT DETECTION CIRCUIT AND METHOD OF DETECTING DEFECTS IN THE SAME [patent_app_type] => utility [patent_app_number] => 17/199955 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199955
Semiconductor device including defect detection circuit and method of detecting defects in the same Mar 11, 2021 Issued
Array ( [id] => 17447923 [patent_doc_number] => 20220068428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => LATCH CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/198659 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198659
Latch circuit and memory device including the same Mar 10, 2021 Issued
Array ( [id] => 17447905 [patent_doc_number] => 20220068410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/196509 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196509
Memory device and method of operating the memory device Mar 8, 2021 Issued
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