Search

Mohammed A. Bashar

Examiner (ID: 5613, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
739
Issued Applications
646
Pending Applications
94
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17956155 [patent_doc_number] => 11482268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Leakage compensation for memory arrays [patent_app_type] => utility [patent_app_number] => 17/387327 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 18167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387327
Leakage compensation for memory arrays Jul 27, 2021 Issued
Array ( [id] => 18645487 [patent_doc_number] => 11769565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/376411 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12850 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376411
Memory device and operating method thereof Jul 14, 2021 Issued
Array ( [id] => 17878383 [patent_doc_number] => 11450404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Memory device including redundancy mats [patent_app_type] => utility [patent_app_number] => 17/370637 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14779 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370637
Memory device including redundancy mats Jul 7, 2021 Issued
Array ( [id] => 18124474 [patent_doc_number] => 20230010086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SYSTEM AND METHOD TO MINIMIZE CODEWORD FAILURE RATE [patent_app_type] => utility [patent_app_number] => 17/370564 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370564
System and method to minimize codeword failure rate Jul 7, 2021 Issued
Array ( [id] => 17637929 [patent_doc_number] => 11348658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory controller and storage device including the same [patent_app_type] => utility [patent_app_number] => 17/359924 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6241 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359924
Memory controller and storage device including the same Jun 27, 2021 Issued
Array ( [id] => 17737756 [patent_doc_number] => 20220223218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY REPAIR USING OPTIMIZED REDUNDANCY UTILIZATION [patent_app_type] => utility [patent_app_number] => 17/356647 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356647
Memory repair using optimized redundancy utilization Jun 23, 2021 Issued
Array ( [id] => 17158793 [patent_doc_number] => 20210319844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => MEMORY TEST METHOD AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 17/355946 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355946 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355946
Memory test method and related device Jun 22, 2021 Issued
Array ( [id] => 17302761 [patent_doc_number] => 20210398600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => MEMORY AND OPERATION METHOD OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/354423 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/354423
Memory and operation method of memory Jun 21, 2021 Issued
Array ( [id] => 17302762 [patent_doc_number] => 20210398601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => DIRECT TESTING OF IN-PACKAGE MEMORY [patent_app_type] => utility [patent_app_number] => 17/349612 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/349612
Direct testing of in-package memory Jun 15, 2021 Issued
Array ( [id] => 18053910 [patent_doc_number] => 11527301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Method for reading and writing and memory device [patent_app_type] => utility [patent_app_number] => 17/342492 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 10228 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/342492
Method for reading and writing and memory device Jun 7, 2021 Issued
Array ( [id] => 17115282 [patent_doc_number] => 20210295879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/340681 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340681
Flexible memory system with a controller and a stack of memory Jun 6, 2021 Issued
Array ( [id] => 17757990 [patent_doc_number] => 11398288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Storage medium-assisted system interface training scheme [patent_app_type] => utility [patent_app_number] => 17/326414 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 14890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326414
Storage medium-assisted system interface training scheme May 20, 2021 Issued
Array ( [id] => 17070415 [patent_doc_number] => 20210272632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MEMORY DEVICE USING COMB-LIKE ROUTING STRUCTURE FOR REDUCED METAL LINE LOADING [patent_app_type] => utility [patent_app_number] => 17/317215 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317215
Memory device using comb-like routing structure for reduced metal line loading May 10, 2021 Issued
Array ( [id] => 18371653 [patent_doc_number] => 11651834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Memory duty-cycle skew management [patent_app_type] => utility [patent_app_number] => 17/316765 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316765
Memory duty-cycle skew management May 10, 2021 Issued
Array ( [id] => 17551343 [patent_doc_number] => 20220122685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/313236 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313236
Semiconductor memory devices and memory systems including the same May 5, 2021 Issued
Array ( [id] => 17963409 [patent_doc_number] => 20220343990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => OPTIMIZING MEMORY ACCESS OPERATION PARAMETERS [patent_app_type] => utility [patent_app_number] => 17/302215 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17302215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/302215
Optimizing memory access operation parameters Apr 26, 2021 Issued
Array ( [id] => 17424092 [patent_doc_number] => 11257553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Flash memory cell and associated high voltage row decoder [patent_app_type] => utility [patent_app_number] => 17/239397 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5859 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239397
Flash memory cell and associated high voltage row decoder Apr 22, 2021 Issued
Array ( [id] => 17963408 [patent_doc_number] => 20220343989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => AUTO-POWER ON MODE FOR BIASED TESTING OF A POWER MANAGEMENT INTEGRATED CIRCUIT (PMIC) [patent_app_type] => utility [patent_app_number] => 17/237875 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237875 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237875
Auto-power on mode for biased testing of a power management integrated circuit (PMIC) Apr 21, 2021 Issued
Array ( [id] => 18013541 [patent_doc_number] => 11505825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Methods of synthesizing DNA [patent_app_type] => utility [patent_app_number] => 17/233186 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 94 [patent_figures_cnt] => 123 [patent_no_of_words] => 62281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233186
Methods of synthesizing DNA Apr 15, 2021 Issued
Array ( [id] => 17529713 [patent_doc_number] => 11302411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks [patent_app_type] => utility [patent_app_number] => 17/219308 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219308
Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks Mar 30, 2021 Issued
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