Search

Mohammed A. Bashar

Examiner (ID: 13174, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
746
Issued Applications
652
Pending Applications
90
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17803100 [patent_doc_number] => 11417409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Electronic devices including a test circuit and methods of operating the electronic devices [patent_app_type] => utility [patent_app_number] => 17/193777 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193777
Electronic devices including a test circuit and methods of operating the electronic devices Mar 4, 2021 Issued
Array ( [id] => 16920570 [patent_doc_number] => 20210193662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => DYNAMIC MEMORY STRUCTURE WITH A SHARED COUNTER ELECTRODE [patent_app_type] => utility [patent_app_number] => 17/191709 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191709
Dynamic memory structure with a shared counter electrode Mar 3, 2021 Issued
Array ( [id] => 17463466 [patent_doc_number] => 20220076772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/178554 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178554
Memory system and method of controlling non-volatile memory Feb 17, 2021 Issued
Array ( [id] => 17085257 [patent_doc_number] => 20210280264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/173446 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173446
Memory system Feb 10, 2021 Issued
Array ( [id] => 17416842 [patent_doc_number] => 20220051746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SOFT BIT REFERENCE LEVEL CALIBRATION [patent_app_type] => utility [patent_app_number] => 17/171617 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171617
Soft bit reference level calibration Feb 8, 2021 Issued
Array ( [id] => 20389119 [patent_doc_number] => 12488852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Read-only memory diagnosis and repair [patent_app_type] => utility [patent_app_number] => 18/273059 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18273059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/273059
Read-only memory diagnosis and repair Jan 28, 2021 Issued
Array ( [id] => 16995180 [patent_doc_number] => 20210233600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => MEMORY CALIBRATION DEVICE, SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/157868 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157868
Memory calibration device, system and method Jan 24, 2021 Issued
Array ( [id] => 18131148 [patent_doc_number] => 11557363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Integrated circuit and test operation method thereof [patent_app_type] => utility [patent_app_number] => 17/150921 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6692 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150921
Integrated circuit and test operation method thereof Jan 14, 2021 Issued
Array ( [id] => 17364975 [patent_doc_number] => 11231996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Semiconductor memory devices, memory systems including the same and methods of operating memory systems [patent_app_type] => utility [patent_app_number] => 17/137535 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 13534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137535
Semiconductor memory devices, memory systems including the same and methods of operating memory systems Dec 29, 2020 Issued
Array ( [id] => 16920098 [patent_doc_number] => 20210193190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => STACKED DRAM DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/135138 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135138
Stacked DRAM device and method of manufacture Dec 27, 2020 Issued
Array ( [id] => 16920156 [patent_doc_number] => 20210193248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => NEAR MISS-BASED REFRESH FOR READ DISTURB MITIGATION [patent_app_type] => utility [patent_app_number] => 17/132902 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132902
NEAR MISS-BASED REFRESH FOR READ DISTURB MITIGATION Dec 22, 2020 Abandoned
Array ( [id] => 17070430 [patent_doc_number] => 20210272647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => DYNAMIC ERROR MONITOR AND REPAIR [patent_app_type] => utility [patent_app_number] => 17/130250 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130250
Dynamic error monitor and repair Dec 21, 2020 Issued
Array ( [id] => 17691895 [patent_doc_number] => 20220199188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => BUILT-IN MEMORY REPAIR WITH REPAIR CODE COMPRESSION [patent_app_type] => utility [patent_app_number] => 17/125323 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125323
Built-in memory repair with repair code compression Dec 16, 2020 Issued
Array ( [id] => 18494052 [patent_doc_number] => 11699473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => FX driver circuit [patent_app_type] => utility [patent_app_number] => 17/111311 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 15075 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111311
FX driver circuit Dec 2, 2020 Issued
Array ( [id] => 17992960 [patent_doc_number] => 20220358997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => WRITE OPERATION ASSIST CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/790281 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17790281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/790281
Write operation assist circuit Nov 18, 2020 Issued
Array ( [id] => 17332212 [patent_doc_number] => 11222680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Memory plate segmentation to reduce operating power [patent_app_type] => utility [patent_app_number] => 17/097738 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097738
Memory plate segmentation to reduce operating power Nov 12, 2020 Issued
Array ( [id] => 17582626 [patent_doc_number] => 20220139481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => ADJUSTING A RELIABILITY SCAN THRESHOLD IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/085445 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085445
Adjusting a reliability scan threshold in a memory sub-system Oct 29, 2020 Issued
Array ( [id] => 16631416 [patent_doc_number] => 20210050069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => MEMORY CIRCUIT DEVICE AND A METHOD FOR TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 17/085051 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085051
Memory circuit device and a method for testing the same Oct 29, 2020 Issued
Array ( [id] => 17224504 [patent_doc_number] => 11177014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Global-local read calibration [patent_app_type] => utility [patent_app_number] => 17/083138 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083138
Global-local read calibration Oct 27, 2020 Issued
Array ( [id] => 17469995 [patent_doc_number] => 11276477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Memory controller and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/080748 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 18011 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080748 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080748
Memory controller and operating method thereof Oct 25, 2020 Issued
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