Search

Mohammed A. Bashar

Examiner (ID: 5613, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
739
Issued Applications
646
Pending Applications
94
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17757993 [patent_doc_number] => 11398291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device [patent_app_type] => utility [patent_app_number] => 17/213675 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 11855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213675
Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device Mar 25, 2021 Issued
Array ( [id] => 17447918 [patent_doc_number] => 20220068423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => Level Dependent Error Correction Code Protection in Multi-Level Non-Volatile Memory [patent_app_type] => utility [patent_app_number] => 17/213486 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213486
Level dependent error correction code protection in multi-level non-volatile memory Mar 25, 2021 Issued
Array ( [id] => 16965984 [patent_doc_number] => 20210217483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => Method, Apparatus and Electronic Device for Texting Memory, and Computer-Readable Storage Medium [patent_app_type] => utility [patent_app_number] => 17/213717 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213717
Method, apparatus and electronic device for texting memory, and computer-readable storage medium Mar 25, 2021 Issued
Array ( [id] => 19781313 [patent_doc_number] => 12230351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => On-chip power regulation circuitry and regulation method thereof [patent_app_type] => utility [patent_app_number] => 17/912766 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5725 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17912766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/912766
On-chip power regulation circuitry and regulation method thereof Mar 24, 2021 Issued
Array ( [id] => 17326279 [patent_doc_number] => 11217304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Memory operation method and circuit [patent_app_type] => utility [patent_app_number] => 17/207114 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207114
Memory operation method and circuit Mar 18, 2021 Issued
Array ( [id] => 17389106 [patent_doc_number] => 20220036958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DEFECT DETECTION CIRCUIT AND METHOD OF DETECTING DEFECTS IN THE SAME [patent_app_type] => utility [patent_app_number] => 17/199955 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199955
Semiconductor device including defect detection circuit and method of detecting defects in the same Mar 11, 2021 Issued
Array ( [id] => 17447923 [patent_doc_number] => 20220068428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => LATCH CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/198659 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198659
Latch circuit and memory device including the same Mar 10, 2021 Issued
Array ( [id] => 17447905 [patent_doc_number] => 20220068410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/196509 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196509
Memory device and method of operating the memory device Mar 8, 2021 Issued
Array ( [id] => 17803100 [patent_doc_number] => 11417409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Electronic devices including a test circuit and methods of operating the electronic devices [patent_app_type] => utility [patent_app_number] => 17/193777 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193777
Electronic devices including a test circuit and methods of operating the electronic devices Mar 4, 2021 Issued
Array ( [id] => 16920570 [patent_doc_number] => 20210193662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => DYNAMIC MEMORY STRUCTURE WITH A SHARED COUNTER ELECTRODE [patent_app_type] => utility [patent_app_number] => 17/191709 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191709
Dynamic memory structure with a shared counter electrode Mar 3, 2021 Issued
Array ( [id] => 17463466 [patent_doc_number] => 20220076772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/178554 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178554
Memory system and method of controlling non-volatile memory Feb 17, 2021 Issued
Array ( [id] => 17085257 [patent_doc_number] => 20210280264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/173446 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173446
Memory system Feb 10, 2021 Issued
Array ( [id] => 17416842 [patent_doc_number] => 20220051746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SOFT BIT REFERENCE LEVEL CALIBRATION [patent_app_type] => utility [patent_app_number] => 17/171617 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171617
Soft bit reference level calibration Feb 8, 2021 Issued
Array ( [id] => 20389119 [patent_doc_number] => 12488852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Read-only memory diagnosis and repair [patent_app_type] => utility [patent_app_number] => 18/273059 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18273059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/273059
Read-only memory diagnosis and repair Jan 28, 2021 Issued
Array ( [id] => 16995180 [patent_doc_number] => 20210233600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => MEMORY CALIBRATION DEVICE, SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/157868 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157868
Memory calibration device, system and method Jan 24, 2021 Issued
Array ( [id] => 18131148 [patent_doc_number] => 11557363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Integrated circuit and test operation method thereof [patent_app_type] => utility [patent_app_number] => 17/150921 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6692 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150921
Integrated circuit and test operation method thereof Jan 14, 2021 Issued
Array ( [id] => 17364975 [patent_doc_number] => 11231996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Semiconductor memory devices, memory systems including the same and methods of operating memory systems [patent_app_type] => utility [patent_app_number] => 17/137535 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 13534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137535
Semiconductor memory devices, memory systems including the same and methods of operating memory systems Dec 29, 2020 Issued
Array ( [id] => 16920098 [patent_doc_number] => 20210193190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => STACKED DRAM DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/135138 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135138
Stacked DRAM device and method of manufacture Dec 27, 2020 Issued
Array ( [id] => 16920156 [patent_doc_number] => 20210193248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => NEAR MISS-BASED REFRESH FOR READ DISTURB MITIGATION [patent_app_type] => utility [patent_app_number] => 17/132902 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132902
NEAR MISS-BASED REFRESH FOR READ DISTURB MITIGATION Dec 22, 2020 Abandoned
Array ( [id] => 17070430 [patent_doc_number] => 20210272647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => DYNAMIC ERROR MONITOR AND REPAIR [patent_app_type] => utility [patent_app_number] => 17/130250 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130250
Dynamic error monitor and repair Dec 21, 2020 Issued
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