Search

Mohammed A. Bashar

Examiner (ID: 5613, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
739
Issued Applications
646
Pending Applications
94
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17691895 [patent_doc_number] => 20220199188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => BUILT-IN MEMORY REPAIR WITH REPAIR CODE COMPRESSION [patent_app_type] => utility [patent_app_number] => 17/125323 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125323
Built-in memory repair with repair code compression Dec 16, 2020 Issued
Array ( [id] => 18494052 [patent_doc_number] => 11699473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => FX driver circuit [patent_app_type] => utility [patent_app_number] => 17/111311 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 15075 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111311
FX driver circuit Dec 2, 2020 Issued
Array ( [id] => 17992960 [patent_doc_number] => 20220358997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => WRITE OPERATION ASSIST CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/790281 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17790281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/790281
Write operation assist circuit Nov 18, 2020 Issued
Array ( [id] => 17332212 [patent_doc_number] => 11222680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Memory plate segmentation to reduce operating power [patent_app_type] => utility [patent_app_number] => 17/097738 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097738
Memory plate segmentation to reduce operating power Nov 12, 2020 Issued
Array ( [id] => 17582626 [patent_doc_number] => 20220139481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => ADJUSTING A RELIABILITY SCAN THRESHOLD IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/085445 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085445
Adjusting a reliability scan threshold in a memory sub-system Oct 29, 2020 Issued
Array ( [id] => 16631416 [patent_doc_number] => 20210050069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => MEMORY CIRCUIT DEVICE AND A METHOD FOR TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 17/085051 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085051
Memory circuit device and a method for testing the same Oct 29, 2020 Issued
Array ( [id] => 17224504 [patent_doc_number] => 11177014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Global-local read calibration [patent_app_type] => utility [patent_app_number] => 17/083138 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083138
Global-local read calibration Oct 27, 2020 Issued
Array ( [id] => 17469995 [patent_doc_number] => 11276477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Memory controller and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/080748 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 18011 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080748 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080748
Memory controller and operating method thereof Oct 25, 2020 Issued
Array ( [id] => 17107226 [patent_doc_number] => 11127450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Pre-writing memory cells of an array [patent_app_type] => utility [patent_app_number] => 17/064116 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064116 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/064116
Pre-writing memory cells of an array Oct 5, 2020 Issued
Array ( [id] => 17825571 [patent_doc_number] => 11430523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Storage device and method for operating the same [patent_app_type] => utility [patent_app_number] => 17/036430 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8188 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036430
Storage device and method for operating the same Sep 28, 2020 Issued
Array ( [id] => 17590513 [patent_doc_number] => 11328788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Method and system for replacement of memory cells [patent_app_type] => utility [patent_app_number] => 17/011991 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011991
Method and system for replacement of memory cells Sep 2, 2020 Issued
Array ( [id] => 17040406 [patent_doc_number] => 20210257042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => MEMORY INSPECTING METHOD AND MEMORY INSPECTING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/009990 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009990
Memory inspecting method and memory inspecting system Sep 1, 2020 Issued
Array ( [id] => 16715389 [patent_doc_number] => 20210082536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/009404 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009404
Semiconductor memory device and storage device Aug 31, 2020 Issued
Array ( [id] => 17239375 [patent_doc_number] => 11183263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Method of error detection in a ternary content addressable memory [patent_app_type] => utility [patent_app_number] => 17/003272 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5923 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003272
Method of error detection in a ternary content addressable memory Aug 25, 2020 Issued
Array ( [id] => 17447922 [patent_doc_number] => 20220068427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR PROBABILISTIC DATA STRUCTURES FOR ERROR TRACKING [patent_app_type] => utility [patent_app_number] => 17/003486 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003486
Apparatuses, systems, and methods for probabilistic data structures for error tracking Aug 25, 2020 Issued
Array ( [id] => 16600025 [patent_doc_number] => 20210026556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => BUFFER CIRCUIT WITH DATA BIT INVERSION [patent_app_type] => utility [patent_app_number] => 16/947679 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947679
Buffer circuit with data bit inversion Aug 11, 2020 Issued
Array ( [id] => 17652478 [patent_doc_number] => 11355214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Debugging memory devices [patent_app_type] => utility [patent_app_number] => 16/989704 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18356 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989704 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989704
Debugging memory devices Aug 9, 2020 Issued
Array ( [id] => 16585817 [patent_doc_number] => 20210020219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => ENABLING FAST PULSE OPERATION [patent_app_type] => utility [patent_app_number] => 16/983455 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983455 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983455
Enabling fast pulse operation Aug 2, 2020 Issued
Array ( [id] => 17469990 [patent_doc_number] => 11276472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Non-volatile memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/935559 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 14783 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/935559
Non-volatile memory device and method of operating the same Jul 21, 2020 Issued
Array ( [id] => 16544649 [patent_doc_number] => 20200411064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY [patent_app_type] => utility [patent_app_number] => 16/927146 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927146
Flexible memory system with a controller and a stack of memory Jul 12, 2020 Issued
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