
Mohammed A. Bashar
Examiner (ID: 5464, Phone: (571)272-2908 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 779 |
| Issued Applications | 680 |
| Pending Applications | 87 |
| Abandoned Applications | 34 |
Applications
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|---|---|---|---|
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