Search

Mohammed A. Bashar

Examiner (ID: 5613, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
739
Issued Applications
646
Pending Applications
94
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16394226 [patent_doc_number] => 20200335167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => MEMORY DEVICE USING COMB-LIKE ROUTING STRUCTURE FOR REDUCED METAL LINE LOADING [patent_app_type] => utility [patent_app_number] => 16/915606 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915606 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915606
Memory device using comb-like routing structure for reduced metal line loading Jun 28, 2020 Issued
Array ( [id] => 16479347 [patent_doc_number] => 10854300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Multi-state programming in memory device with loop-dependent bit line voltage during verify [patent_app_type] => utility [patent_app_number] => 16/898145 [patent_app_country] => US [patent_app_date] => 2020-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 18387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898145 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/898145
Multi-state programming in memory device with loop-dependent bit line voltage during verify Jun 9, 2020 Issued
Array ( [id] => 16330813 [patent_doc_number] => 20200301779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/894115 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16894115 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/894115
Semiconductor memory devices, memory systems including the same and methods of operating memory systems Jun 4, 2020 Issued
Array ( [id] => 16315863 [patent_doc_number] => 20200294601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/891455 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891455 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891455
Memory device Jun 2, 2020 Issued
Array ( [id] => 16707433 [patent_doc_number] => 10957375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Dynamic random access memory (DRAM) cell, DRAM device and storage method [patent_app_type] => utility [patent_app_number] => 16/883635 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883635
Dynamic random access memory (DRAM) cell, DRAM device and storage method May 25, 2020 Issued
Array ( [id] => 16300846 [patent_doc_number] => 20200286569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => FLASH MEMORY CELL AND ASSOCIATED HIGH VOLTAGE ROW DECODER [patent_app_type] => utility [patent_app_number] => 16/879663 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/879663
Flash memory cell and associated high voltage row decoder May 19, 2020 Issued
Array ( [id] => 17469971 [patent_doc_number] => 11276453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Periodic calibrations during memory device self refresh [patent_app_type] => utility [patent_app_number] => 16/879583 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3458 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/879583
Periodic calibrations during memory device self refresh May 19, 2020 Issued
Array ( [id] => 17172580 [patent_doc_number] => 20210326250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => Keeping Zones Open With Intermediate Padding [patent_app_type] => utility [patent_app_number] => 16/853408 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853408 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853408
Keeping zones open with intermediate padding Apr 19, 2020 Issued
Array ( [id] => 18607140 [patent_doc_number] => 11748608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Analog neural network systems [patent_app_type] => utility [patent_app_number] => 16/844551 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9598 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844551
Analog neural network systems Apr 8, 2020 Issued
Array ( [id] => 16432692 [patent_doc_number] => 10832785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Non-volatile memory with countermeasure for program disturb including purge during precharge [patent_app_type] => utility [patent_app_number] => 16/840156 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 18607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840156
Non-volatile memory with countermeasure for program disturb including purge during precharge Apr 2, 2020 Issued
Array ( [id] => 16177296 [patent_doc_number] => 20200224264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SYSTEMS AND METHODS FOR WRITING, READING, AND CONTROLLING DATA STORED IN A POLYMER [patent_app_type] => utility [patent_app_number] => 16/836689 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 62199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -48 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836689
Systems and methods for writing, reading, and controlling data stored in a polymer Mar 30, 2020 Issued
Array ( [id] => 19356153 [patent_doc_number] => 12056601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Circuitry to compensate for data drift in analog neural memory in an artificial neural network [patent_app_type] => utility [patent_app_number] => 16/830733 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 55 [patent_no_of_words] => 14514 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830733 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830733
Circuitry to compensate for data drift in analog neural memory in an artificial neural network Mar 25, 2020 Issued
Array ( [id] => 16616961 [patent_doc_number] => 20210035614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => CONTROL OF DUAL-VOLTAGE MEMORY OPERATION [patent_app_type] => utility [patent_app_number] => 16/820828 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/820828
Control of dual-voltage memory operation Mar 16, 2020 Issued
Array ( [id] => 16097851 [patent_doc_number] => 20200202912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/809127 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809127 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809127
Semiconductor device Mar 3, 2020 Issued
Array ( [id] => 16552782 [patent_doc_number] => 10885946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Stacked DRAM device and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/801990 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/801990
Stacked DRAM device and method of manufacture Feb 25, 2020 Issued
Array ( [id] => 17438770 [patent_doc_number] => 11264110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Refresh operations for memory cells based on susceptibility to read errors [patent_app_type] => utility [patent_app_number] => 16/790362 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 16121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/790362
Refresh operations for memory cells based on susceptibility to read errors Feb 12, 2020 Issued
Array ( [id] => 18750668 [patent_doc_number] => 11809982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Performance and area efficient synapse memory cell structure [patent_app_type] => utility [patent_app_number] => 16/782758 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5969 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782758
Performance and area efficient synapse memory cell structure Feb 4, 2020 Issued
Array ( [id] => 17772166 [patent_doc_number] => 11404117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Self-selecting memory array with horizontal access lines [patent_app_type] => utility [patent_app_number] => 16/781958 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 24661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781958
Self-selecting memory array with horizontal access lines Feb 3, 2020 Issued
Array ( [id] => 16210169 [patent_doc_number] => 20200243159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => STACKED MEMORY APPARATUS USING ERROR CORRECTION CODE AND REPAIRING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/750923 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16750923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/750923
Stacked memory apparatus using error correction code and repairing method thereof Jan 22, 2020 Issued
Array ( [id] => 15938579 [patent_doc_number] => 20200160923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => MEMORY CONTROLLER FOR CONTROLLING MEMORY DEVICE BASED ON ERASE STATE INFORMATION AND METHOD OF OPERATING THE MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/747790 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747790
Memory controller for controlling memory device based on erase state information and method of operating the memory controller Jan 20, 2020 Issued
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