Search

Mohammed A. Bashar

Examiner (ID: 5464, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
779
Issued Applications
680
Pending Applications
87
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17438770 [patent_doc_number] => 11264110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Refresh operations for memory cells based on susceptibility to read errors [patent_app_type] => utility [patent_app_number] => 16/790362 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 16121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/790362
Refresh operations for memory cells based on susceptibility to read errors Feb 12, 2020 Issued
Array ( [id] => 18750668 [patent_doc_number] => 11809982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Performance and area efficient synapse memory cell structure [patent_app_type] => utility [patent_app_number] => 16/782758 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5969 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782758
Performance and area efficient synapse memory cell structure Feb 4, 2020 Issued
Array ( [id] => 17772166 [patent_doc_number] => 11404117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Self-selecting memory array with horizontal access lines [patent_app_type] => utility [patent_app_number] => 16/781958 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 24661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781958
Self-selecting memory array with horizontal access lines Feb 3, 2020 Issued
Array ( [id] => 16210169 [patent_doc_number] => 20200243159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => STACKED MEMORY APPARATUS USING ERROR CORRECTION CODE AND REPAIRING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/750923 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16750923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/750923
Stacked memory apparatus using error correction code and repairing method thereof Jan 22, 2020 Issued
Array ( [id] => 15938579 [patent_doc_number] => 20200160923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => MEMORY CONTROLLER FOR CONTROLLING MEMORY DEVICE BASED ON ERASE STATE INFORMATION AND METHOD OF OPERATING THE MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/747790 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747790
Memory controller for controlling memory device based on erase state information and method of operating the memory controller Jan 20, 2020 Issued
Array ( [id] => 16987780 [patent_doc_number] => 11074959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => DDR memory bus with a reduced data strobe signal preamble timespan [patent_app_type] => utility [patent_app_number] => 16/741368 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4811 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741368 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741368
DDR memory bus with a reduced data strobe signal preamble timespan Jan 12, 2020 Issued
Array ( [id] => 17500449 [patent_doc_number] => 11289159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Memory device and method for writing data [patent_app_type] => utility [patent_app_number] => 16/720406 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10583 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720406
Memory device and method for writing data Dec 18, 2019 Issued
Array ( [id] => 17818331 [patent_doc_number] => 11423952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Multi-chip devices [patent_app_type] => utility [patent_app_number] => 16/715249 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 11419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715249
Multi-chip devices Dec 15, 2019 Issued
Array ( [id] => 16048135 [patent_doc_number] => 10685952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Strapping structure of memory circuit [patent_app_type] => utility [patent_app_number] => 16/704404 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704404
Strapping structure of memory circuit Dec 4, 2019 Issued
Array ( [id] => 16096439 [patent_doc_number] => 20200202206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => Artificial neuron for neuromorphic chip with resistive synapses [patent_app_type] => utility [patent_app_number] => 16/703465 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703465
Artificial neuron for neuromorphic chip with resistive synapses Dec 3, 2019 Issued
Array ( [id] => 16308433 [patent_doc_number] => 10777236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Methods and apparatuses of driver circuits without voltage level shifters [patent_app_type] => utility [patent_app_number] => 16/696246 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696246
Methods and apparatuses of driver circuits without voltage level shifters Nov 25, 2019 Issued
Array ( [id] => 17818364 [patent_doc_number] => 11423985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Devices and methods for controlling write operations [patent_app_type] => utility [patent_app_number] => 16/582743 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7862 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582743 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582743
Devices and methods for controlling write operations Sep 24, 2019 Issued
Array ( [id] => 18912881 [patent_doc_number] => 11875866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Memory programming methods and memory systems [patent_app_type] => utility [patent_app_number] => 16/581067 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5917 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/581067
Memory programming methods and memory systems Sep 23, 2019 Issued
Array ( [id] => 15414371 [patent_doc_number] => 20200027508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => Nonvolatile Digital Computing with Ferroelectric FET [patent_app_type] => utility [patent_app_number] => 16/580256 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/580256
Nonvolatile digital computing with ferroelectric FET Sep 23, 2019 Issued
Array ( [id] => 17492098 [patent_doc_number] => 11281401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Controlled heating of a memory device [patent_app_type] => utility [patent_app_number] => 16/579437 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 32979 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579437 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579437
Controlled heating of a memory device Sep 22, 2019 Issued
Array ( [id] => 15328271 [patent_doc_number] => 20200004465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => CORRECTING POWER LOSS IN NAND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/566545 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566545 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566545
Correcting power loss in NAND memory devices Sep 9, 2019 Issued
Array ( [id] => 15331081 [patent_doc_number] => 20200005870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => MEMORY START VOLTAGE MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/566713 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566713
Memory start voltage management Sep 9, 2019 Issued
Array ( [id] => 17283911 [patent_doc_number] => 11200951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/561391 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 43 [patent_no_of_words] => 16870 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561391 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561391
Semiconductor memory device Sep 4, 2019 Issued
Array ( [id] => 16675483 [patent_doc_number] => 20210064249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => EXTENDING THE LIFE OF A SOLID STATE DRIVE BY USING MLC FLASH BLOCKS IN SLC MODE [patent_app_type] => utility [patent_app_number] => 16/560858 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560858
Extending the life of a solid state drive by using MLC flash blocks in SLC mode Sep 3, 2019 Issued
Array ( [id] => 16677038 [patent_doc_number] => 20210065804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => MEMORY DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/558747 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558747
Memory device and control method thereof Sep 2, 2019 Issued
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