Search

Mohammed A. Bashar

Examiner (ID: 5613, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
739
Issued Applications
646
Pending Applications
94
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16660372 [patent_doc_number] => 20210057009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => WORD LINE DRIVER CIRCUITRY, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/548242 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548242 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548242
Word line driver circuitry, and associated methods, devices, and systems Aug 21, 2019 Issued
Array ( [id] => 15717149 [patent_doc_number] => 20200105342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => PHASE CHANGE MEMORY OPERATION METHOD AND CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/547106 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547106
Phase change memory operation method and circuit Aug 20, 2019 Issued
Array ( [id] => 16080199 [patent_doc_number] => 20200194086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/547416 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547416
Non-volatile memory device and method of operating the same Aug 20, 2019 Issued
Array ( [id] => 16386254 [patent_doc_number] => 10811095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 16/546614 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546614
Semiconductor storage device Aug 20, 2019 Issued
Array ( [id] => 15458817 [patent_doc_number] => 20200042233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => BUFFER CIRCUIT WITH DATA BIT INVERSION [patent_app_type] => utility [patent_app_number] => 16/543870 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543870
Buffer circuit with data bit inversion Aug 18, 2019 Issued
Array ( [id] => 16417601 [patent_doc_number] => 10825501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Pre-writing memory cells of an array [patent_app_type] => utility [patent_app_number] => 16/537090 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537090 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537090
Pre-writing memory cells of an array Aug 8, 2019 Issued
Array ( [id] => 16479315 [patent_doc_number] => 10854268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory plate segmentation to reduce operating power [patent_app_type] => utility [patent_app_number] => 16/536141 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536141
Memory plate segmentation to reduce operating power Aug 7, 2019 Issued
Array ( [id] => 15563853 [patent_doc_number] => 20200066338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => RESISTANCE CHANGE DEVICE, MANUFACTURING METHOD FOR THE SAME, AND STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 16/533735 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533735 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533735
Resistance change device, manufacturing method for the same, and storage apparatus Aug 5, 2019 Issued
Array ( [id] => 15905487 [patent_doc_number] => 20200152264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => MEMORY DEVICE, MEMORY CELL AND METHOD FOR PROGRAMMING MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/530517 [patent_app_country] => US [patent_app_date] => 2019-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16530517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/530517
Memory device, memory cell and method for programming memory cell Aug 1, 2019 Issued
Array ( [id] => 15153905 [patent_doc_number] => 20190355430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/528318 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528318 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528318
Memory device and memory system Jul 30, 2019 Issued
Array ( [id] => 15937047 [patent_doc_number] => 20200160157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => MEMORY DEVICE INCLUDING ARITHMETIC CIRCUIT AND NEURAL NETWORK SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/522920 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522920 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522920
Memory device including arithmetic circuit and neural network system including the same Jul 25, 2019 Issued
Array ( [id] => 17085258 [patent_doc_number] => 20210280265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/250417 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250417 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250417
Memory circuit Jul 24, 2019 Issued
Array ( [id] => 16172602 [patent_doc_number] => 10714178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Methods, compositions, and devices for information storage [patent_app_type] => utility [patent_app_number] => 16/514726 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 89 [patent_no_of_words] => 50470 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514726
Methods, compositions, and devices for information storage Jul 16, 2019 Issued
Array ( [id] => 17077760 [patent_doc_number] => 11114173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Semiconductor memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/510508 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 9635 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510508 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/510508
Semiconductor memory device and method of operating the same Jul 11, 2019 Issued
Array ( [id] => 16147645 [patent_doc_number] => 10706897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Read threshold voltage selection [patent_app_type] => utility [patent_app_number] => 16/459953 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459953 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459953
Read threshold voltage selection Jul 1, 2019 Issued
Array ( [id] => 16528512 [patent_doc_number] => 20200402593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => DYNAMIC SWITCHING FOR IMPROVED POWER UTILIZATION [patent_app_type] => utility [patent_app_number] => 16/444671 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444671
Dynamic switching for improved power utilization Jun 17, 2019 Issued
Array ( [id] => 15388925 [patent_doc_number] => 10535661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Integrated memory and integrated assemblies [patent_app_type] => utility [patent_app_number] => 16/429486 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5370 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429486
Integrated memory and integrated assemblies Jun 2, 2019 Issued
Array ( [id] => 17637926 [patent_doc_number] => 11348655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory device with analog measurement mode features [patent_app_type] => utility [patent_app_number] => 16/625371 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5770 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625371
Memory device with analog measurement mode features May 30, 2019 Issued
Array ( [id] => 15611015 [patent_doc_number] => 10586574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Word line cache mode [patent_app_type] => utility [patent_app_number] => 16/428745 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/428745
Word line cache mode May 30, 2019 Issued
Array ( [id] => 17246820 [patent_doc_number] => 20210366565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => MEMORY COMPONENT PROVIDED WITH A TEST INTERFACE [patent_app_type] => utility [patent_app_number] => 16/625234 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625234 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625234
Memory component provided with a test interface May 30, 2019 Issued
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