Search

Mohammed A. Bashar

Examiner (ID: 13174, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
746
Issued Applications
652
Pending Applications
90
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20167647 [patent_doc_number] => 20250259694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => MEMORY INCLUDING SENSE AMPLIFIER AND OPERATION METHOD OF MEMORY [patent_app_type] => utility [patent_app_number] => 18/665595 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665595
MEMORY INCLUDING SENSE AMPLIFIER AND OPERATION METHOD OF MEMORY May 15, 2024 Pending
Array ( [id] => 19803757 [patent_doc_number] => 20250069682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY DEVICE INCLUDING REPAIR CIRCUIT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/665817 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665817
MEMORY DEVICE INCLUDING REPAIR CIRCUIT AND OPERATING METHOD THEREOF May 15, 2024 Pending
Array ( [id] => 20352528 [patent_doc_number] => 20250349380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE TESTING APPARATUS AND SEMICONDUCTOR DEVICE TESTING METHOD [patent_app_type] => utility [patent_app_number] => 18/658275 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658275
SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE TESTING APPARATUS AND SEMICONDUCTOR DEVICE TESTING METHOD May 7, 2024 Pending
Array ( [id] => 20036075 [patent_doc_number] => 20250174297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/653688 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653688
STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICE May 1, 2024 Pending
Array ( [id] => 19559668 [patent_doc_number] => 20240371460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEQUENTIAL ACCESS TO LINKED MEMORY DICE FOR BUS TRAINING [patent_app_type] => utility [patent_app_number] => 18/651357 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651357 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/651357
SEQUENTIAL ACCESS TO LINKED MEMORY DICE FOR BUS TRAINING Apr 29, 2024 Pending
Array ( [id] => 19574892 [patent_doc_number] => 20240379184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/650942 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650942 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650942
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME Apr 29, 2024 Pending
Array ( [id] => 19384355 [patent_doc_number] => 20240274225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => METHOD FOR PERFORMING AGING TEST ON SEMICONDUCTOR USED FOR NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/648655 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648655
METHOD FOR PERFORMING AGING TEST ON SEMICONDUCTOR USED FOR NEURAL NETWORK Apr 28, 2024 Pending
Array ( [id] => 20324372 [patent_doc_number] => 20250336460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => VARIABLE RESISTANCE FOR CURRENT CONTROL IN NONVOLATILE MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 18/648506 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648506
VARIABLE RESISTANCE FOR CURRENT CONTROL IN NONVOLATILE MEMORY ARRAYS Apr 28, 2024 Pending
Array ( [id] => 19546151 [patent_doc_number] => 20240363187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN [patent_app_type] => utility [patent_app_number] => 18/635569 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635569
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN Apr 14, 2024 Pending
Array ( [id] => 20297654 [patent_doc_number] => 20250322897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => DUMMY MEMORY HOLE DEFECT DETECTION [patent_app_type] => utility [patent_app_number] => 18/635219 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635219
DUMMY MEMORY HOLE DEFECT DETECTION Apr 14, 2024 Pending
Array ( [id] => 19546155 [patent_doc_number] => 20240363191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Usage-Based Disturbance Counter Repair [patent_app_type] => utility [patent_app_number] => 18/634096 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634096
Usage-Based Disturbance Counter Repair Apr 11, 2024 Pending
Array ( [id] => 19483752 [patent_doc_number] => 20240331794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => APPARATUSES AND METHODS FOR TESTING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/612284 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612284
APPARATUSES AND METHODS FOR TESTING MEMORY DEVICES Mar 20, 2024 Pending
Array ( [id] => 20250897 [patent_doc_number] => 20250299766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => VOTING-BASED STATE SELECTION FOR A VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/611351 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611351
VOTING-BASED STATE SELECTION FOR A VOLATILE MEMORY Mar 19, 2024 Pending
Array ( [id] => 19285381 [patent_doc_number] => 20240221858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DYNAMIC ERROR MONITOR AND REPAIR [patent_app_type] => utility [patent_app_number] => 18/608220 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608220
Dynamic error monitor and repair Mar 17, 2024 Issued
Array ( [id] => 20002111 [patent_doc_number] => 20250140333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION [patent_app_type] => utility [patent_app_number] => 18/596939 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596939
SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION Mar 5, 2024 Pending
Array ( [id] => 19363919 [patent_doc_number] => 20240265953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE [patent_app_type] => utility [patent_app_number] => 18/581694 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581694 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581694
Area-efficient, width-adjustable signaling interface Feb 19, 2024 Issued
Array ( [id] => 20002112 [patent_doc_number] => 20250140334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR DEVICES RELATED TO PRECHARGE OPERATION [patent_app_type] => utility [patent_app_number] => 18/442866 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442866
SEMICONDUCTOR DEVICES RELATED TO PRECHARGE OPERATION Feb 14, 2024 Pending
Array ( [id] => 19384353 [patent_doc_number] => 20240274223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA [patent_app_type] => utility [patent_app_number] => 18/430406 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430406
APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA Jan 31, 2024 Pending
Array ( [id] => 19321195 [patent_doc_number] => 20240242741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => STACKED DRAM DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 18/420688 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420688
Stacked DRAM device and method of manufacture Jan 22, 2024 Issued
Array ( [id] => 20124286 [patent_doc_number] => 20250239317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => PRE-CHARACTERIZING WEAK BITS FOR INCREASED LOW DENSITY PARITY CHECK (LDPC) SPEED [patent_app_type] => utility [patent_app_number] => 18/415722 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415722 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415722
PRE-CHARACTERIZING WEAK BITS FOR INCREASED LOW DENSITY PARITY CHECK (LDPC) SPEED Jan 17, 2024 Pending
Menu