Search

Mohammed A. Bashar

Examiner (ID: 5464, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
779
Issued Applications
680
Pending Applications
87
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19604424 [patent_doc_number] => 20240395304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/789866 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789866
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME Jul 30, 2024 Pending
Array ( [id] => 20283352 [patent_doc_number] => 20250308594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => PROGRAM OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/789613 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789613
PROGRAM OPERATIONS IN MEMORY DEVICES Jul 29, 2024 Pending
Array ( [id] => 19893036 [patent_doc_number] => 20250118348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => CRITICAL TIMING DRIVEN DYNAMIC VOLTAGE FREQUENCY SCALING BASED ON AN AT-SPEED SCAN [patent_app_type] => utility [patent_app_number] => 18/787824 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787824
CRITICAL TIMING DRIVEN DYNAMIC VOLTAGE FREQUENCY SCALING BASED ON AN AT-SPEED SCAN Jul 28, 2024 Pending
Array ( [id] => 19711594 [patent_doc_number] => 20250021736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => DUMMY CELLS PLACED ADJACENT FUNCTIONAL BLOCKS [patent_app_type] => utility [patent_app_number] => 18/785611 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785611
DUMMY CELLS PLACED ADJACENT FUNCTIONAL BLOCKS Jul 25, 2024 Pending
Array ( [id] => 20053416 [patent_doc_number] => 20250191638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/781037 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781037 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781037
SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT Jul 22, 2024 Pending
Array ( [id] => 20291073 [patent_doc_number] => 20250316316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/772931 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772931
SEMICONDUCTOR DEVICE Jul 14, 2024 Pending
Array ( [id] => 20476000 [patent_doc_number] => 20260018221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => UNIFORM RANDOMNESS FOR PROGRAM-ERASE CYCLES USING MULTI-BIT INVERSION SEEDS [patent_app_type] => utility [patent_app_number] => 18/773314 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773314 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773314
UNIFORM RANDOMNESS FOR PROGRAM-ERASE CYCLES USING MULTI-BIT INVERSION SEEDS Jul 14, 2024 Pending
Array ( [id] => 19726889 [patent_doc_number] => 20250029640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MEMORY DEVICE RELATED TO SIGNAL TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/770360 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770360
MEMORY DEVICE RELATED TO SIGNAL TRANSMISSION Jul 10, 2024 Pending
Array ( [id] => 20167621 [patent_doc_number] => 20250259668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => BIT-LINE SENSE AMPLIIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/765195 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765195
BIT-LINE SENSE AMPLIIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Jul 4, 2024 Pending
Array ( [id] => 20153149 [patent_doc_number] => 20250252987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/763876 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763876
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE Jul 2, 2024 Pending
Array ( [id] => 19712364 [patent_doc_number] => 20250022506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SELF-TIMING READ TERMINATION [patent_app_type] => utility [patent_app_number] => 18/763964 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763964
Self-timing read termination Jul 2, 2024 Issued
Array ( [id] => 19749190 [patent_doc_number] => 20250037755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SELECTION CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/763395 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763395
SELECTION CIRCUITRY Jul 2, 2024 Pending
Array ( [id] => 19865998 [patent_doc_number] => 20250104784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => NON-VOLATILE MEMORY SYSTEM AND DATA RECOVER READ OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/762272 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762272
NON-VOLATILE MEMORY SYSTEM AND DATA RECOVER READ OPERATION METHOD THEREOF Jul 1, 2024 Pending
Array ( [id] => 19951096 [patent_doc_number] => 12322466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Memory device with redundancy for page-based repair [patent_app_type] => utility [patent_app_number] => 18/761619 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761619
Memory device with redundancy for page-based repair Jul 1, 2024 Issued
Array ( [id] => 20461929 [patent_doc_number] => 20260011358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => Efficient Coordination of Error Handling and Usage-Based-Disturbance Mitigation [patent_app_type] => utility [patent_app_number] => 18/762054 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762054 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762054
Efficient Coordination of Error Handling and Usage-Based-Disturbance Mitigation Jul 1, 2024 Pending
Array ( [id] => 20667394 [patent_doc_number] => 12609174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Memory device and read voltage setting method thereof [patent_app_type] => utility [patent_app_number] => 18/761321 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 1207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761321
Memory device and read voltage setting method thereof Jul 1, 2024 Issued
Array ( [id] => 20222770 [patent_doc_number] => 20250285701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => SYSTEM, MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/762155 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762155
SYSTEM, MEMORY DEVICE AND METHOD Jul 1, 2024 Pending
Array ( [id] => 20036063 [patent_doc_number] => 20250174285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MANAGING REFRESHMENT OF MEMORY CELLS IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/761275 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761275
MANAGING REFRESHMENT OF MEMORY CELLS IN MEMORY SYSTEMS Jun 30, 2024 Pending
Array ( [id] => 19696120 [patent_doc_number] => 20250014665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/759105 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759105
TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE Jun 27, 2024 Issued
Array ( [id] => 20448123 [patent_doc_number] => 20260004848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => DIFFERENTIAL WRITE AND READ FOR SELECTOR ONLY MEMORY [patent_app_type] => utility [patent_app_number] => 18/757129 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757129 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757129
DIFFERENTIAL WRITE AND READ FOR SELECTOR ONLY MEMORY Jun 26, 2024 Pending
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