Search

Mohammed A. Bashar

Examiner (ID: 2506)

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
765
Issued Applications
669
Pending Applications
85
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20153149 [patent_doc_number] => 20250252987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/763876 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763876
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE Jul 2, 2024 Pending
Array ( [id] => 20463692 [patent_doc_number] => 20260013124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => MEMORY CELL AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/763861 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763861
MEMORY CELL AND METHOD FOR FABRICATING THE SAME Jul 2, 2024 Pending
Array ( [id] => 19951096 [patent_doc_number] => 12322466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Memory device with redundancy for page-based repair [patent_app_type] => utility [patent_app_number] => 18/761619 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761619
Memory device with redundancy for page-based repair Jul 1, 2024 Issued
Array ( [id] => 19865998 [patent_doc_number] => 20250104784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => NON-VOLATILE MEMORY SYSTEM AND DATA RECOVER READ OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/762272 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762272
NON-VOLATILE MEMORY SYSTEM AND DATA RECOVER READ OPERATION METHOD THEREOF Jul 1, 2024 Pending
Array ( [id] => 20461929 [patent_doc_number] => 20260011358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => Efficient Coordination of Error Handling and Usage-Based-Disturbance Mitigation [patent_app_type] => utility [patent_app_number] => 18/762054 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762054 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762054
Efficient Coordination of Error Handling and Usage-Based-Disturbance Mitigation Jul 1, 2024 Pending
Array ( [id] => 20667394 [patent_doc_number] => 12609174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Memory device and read voltage setting method thereof [patent_app_type] => utility [patent_app_number] => 18/761321 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 1207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761321
Memory device and read voltage setting method thereof Jul 1, 2024 Issued
Array ( [id] => 20036063 [patent_doc_number] => 20250174285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MANAGING REFRESHMENT OF MEMORY CELLS IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/761275 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761275
MANAGING REFRESHMENT OF MEMORY CELLS IN MEMORY SYSTEMS Jun 30, 2024 Pending
Array ( [id] => 19696120 [patent_doc_number] => 20250014665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/759105 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759105
TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE Jun 27, 2024 Pending
Array ( [id] => 19866006 [patent_doc_number] => 20250104792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => APPARATUS INCLUDING BTI CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/751936 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751936 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751936
APPARATUS INCLUDING BTI CONTROLLER Jun 23, 2024 Pending
Array ( [id] => 20250891 [patent_doc_number] => 20250299760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => Scannable Memory Subsystem [patent_app_type] => utility [patent_app_number] => 18/752638 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752638 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752638
Scannable Memory Subsystem Jun 23, 2024 Pending
Array ( [id] => 20132102 [patent_doc_number] => 12374419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Method and system for replacement of memory cells [patent_app_type] => utility [patent_app_number] => 18/749098 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749098
Method and system for replacement of memory cells Jun 19, 2024 Issued
Array ( [id] => 20132101 [patent_doc_number] => 12374418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Techniques for detecting a state of a bus [patent_app_type] => utility [patent_app_number] => 18/742749 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742749 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742749
Techniques for detecting a state of a bus Jun 12, 2024 Issued
Array ( [id] => 19646276 [patent_doc_number] => 20240420796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => DISTRIBUTED MRAM CONFIGURATION BIT AND METHOD OF REPAIR [patent_app_type] => utility [patent_app_number] => 18/739969 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739969
DISTRIBUTED MRAM CONFIGURATION BIT AND METHOD OF REPAIR Jun 10, 2024 Pending
Array ( [id] => 19467708 [patent_doc_number] => 20240321378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => BUILT-IN MEMORY REPAIR WITH REPAIR CODE COMPRESSION [patent_app_type] => utility [patent_app_number] => 18/736779 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/736779
Built-in memory repair with repair code compression Jun 6, 2024 Issued
Array ( [id] => 20182108 [patent_doc_number] => 20250266066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => MEMORY DEVICES CONFIGURED TO PERFORM READ OPERATIONS FOR PSEUDO CHANNELS [patent_app_type] => utility [patent_app_number] => 18/675833 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675833
MEMORY DEVICES CONFIGURED TO PERFORM READ OPERATIONS FOR PSEUDO CHANNELS May 27, 2024 Pending
Array ( [id] => 20088589 [patent_doc_number] => 20250218525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR CHIP THAT ADJUSTS STROBE SIGNAL DELAY [patent_app_type] => utility [patent_app_number] => 18/675660 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675660 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675660
SEMICONDUCTOR CHIP THAT ADJUSTS STROBE SIGNAL DELAY May 27, 2024 Pending
Array ( [id] => 19604475 [patent_doc_number] => 20240395355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/671964 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671964
MEMORY DEVICE May 21, 2024 Pending
Array ( [id] => 20019344 [patent_doc_number] => 20250157566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MEMORY SYSTEMS AND DEVICES HAVING ENHANCED COLUMN REPAIR CAPABILITY AND METHODS OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/670883 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670883
MEMORY SYSTEMS AND DEVICES HAVING ENHANCED COLUMN REPAIR CAPABILITY AND METHODS OF OPERATING SAME May 21, 2024 Pending
Array ( [id] => 20596313 [patent_doc_number] => 12580036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Apparatuses and methods for forcing memory cell failures in a memory device [patent_app_type] => utility [patent_app_number] => 18/667358 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7496 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667358
Apparatuses and methods for forcing memory cell failures in a memory device May 16, 2024 Issued
Array ( [id] => 20167647 [patent_doc_number] => 20250259694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => MEMORY INCLUDING SENSE AMPLIFIER AND OPERATION METHOD OF MEMORY [patent_app_type] => utility [patent_app_number] => 18/665595 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665595
MEMORY INCLUDING SENSE AMPLIFIER AND OPERATION METHOD OF MEMORY May 15, 2024 Pending
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