Search

Mohammed A. Bashar

Examiner (ID: 5464, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
779
Issued Applications
680
Pending Applications
87
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14491555 [patent_doc_number] => 10332575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Signal training for prevention of metastability due to clocking indeterminacy [patent_app_type] => utility [patent_app_number] => 15/826404 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826404
Signal training for prevention of metastability due to clocking indeterminacy Nov 28, 2017 Issued
Array ( [id] => 12738211 [patent_doc_number] => 20180137904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => THREE TERMINAL SOT MEMORY CELL WITH ANOMALOUS HALL EFFECT [patent_app_type] => utility [patent_app_number] => 15/822500 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822500 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822500
Three terminal SOT memory cell with anomalous hall effect Nov 26, 2017 Issued
Array ( [id] => 14267265 [patent_doc_number] => 10283202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-07 [patent_title] => Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming [patent_app_type] => utility [patent_app_number] => 15/814772 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 40 [patent_no_of_words] => 22025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814772
Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming Nov 15, 2017 Issued
Array ( [id] => 14333441 [patent_doc_number] => 10297750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Wraparound top electrode line for crossbar array resistive switching device [patent_app_type] => utility [patent_app_number] => 15/814932 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814932 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814932
Wraparound top electrode line for crossbar array resistive switching device Nov 15, 2017 Issued
Array ( [id] => 13629259 [patent_doc_number] => 20180366182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/810820 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810820 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810820
Semiconductor devices Nov 12, 2017 Issued
Array ( [id] => 13228377 [patent_doc_number] => 10127967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-13 [patent_title] => DRAM and method for operating the same [patent_app_type] => utility [patent_app_number] => 15/808448 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6307 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808448
DRAM and method for operating the same Nov 8, 2017 Issued
Array ( [id] => 14282255 [patent_doc_number] => 20190138412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => APPARATUSES AND METHODS FOR REPAIRING MEMORY DEVICES INCLUDING A PLURALITY OF MEMORY DIE AND AN INTERFACE [patent_app_type] => utility [patent_app_number] => 15/808771 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808771
Apparatus and methods for repairing memory devices including a plurality of memory die and an interface Nov 8, 2017 Issued
Array ( [id] => 15611083 [patent_doc_number] => 10586608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => DRAM refresh method, apparatus, and system [patent_app_type] => utility [patent_app_number] => 15/802781 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802781 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802781
DRAM refresh method, apparatus, and system Nov 2, 2017 Issued
Array ( [id] => 13471027 [patent_doc_number] => 20180287056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => SYNAPSE AND SYNAPSE ARRAY [patent_app_type] => utility [patent_app_number] => 15/799649 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799649
SYNAPSE AND SYNAPSE ARRAY Oct 30, 2017 Abandoned
Array ( [id] => 13173535 [patent_doc_number] => 10102887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Area-efficient, width-adjustable signaling interface [patent_app_type] => utility [patent_app_number] => 15/793029 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 12512 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793029
Area-efficient, width-adjustable signaling interface Oct 24, 2017 Issued
Array ( [id] => 13111551 [patent_doc_number] => 10074433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-11 [patent_title] => Data encoding method, memory control circuit unit and memory storage device [patent_app_type] => utility [patent_app_number] => 15/786604 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11731 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786604
Data encoding method, memory control circuit unit and memory storage device Oct 17, 2017 Issued
Array ( [id] => 12848389 [patent_doc_number] => 20180174636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => DATA ALIGNMENT CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE, A SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF ALIGNING DATA IN A SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/787101 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15787101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/787101
Data alignment circuit of a semiconductor memory device, a semiconductor memory device and a method of aligning data in a semiconductor memory device Oct 17, 2017 Issued
Array ( [id] => 14768703 [patent_doc_number] => 10395752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Margin test for multiple-time programmable memory (MTPM) with split wordlines [patent_app_type] => utility [patent_app_number] => 15/730078 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730078
Margin test for multiple-time programmable memory (MTPM) with split wordlines Oct 10, 2017 Issued
Array ( [id] => 13594991 [patent_doc_number] => 20180349044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Programming Schemes for Avoidance or Recovery from Cross-Temperature Read Failures [patent_app_type] => utility [patent_app_number] => 15/716703 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716703 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716703
Programming schemes for avoidance or recovery from cross-temperature read failures Sep 26, 2017 Issued
Array ( [id] => 13304159 [patent_doc_number] => 20180203616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/715271 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715271
Nonvolatile memory device and operating method thereof Sep 25, 2017 Issued
Array ( [id] => 15400717 [patent_doc_number] => 10541018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => DDR memory bus with a reduced data strobe signal preamble timespan [patent_app_type] => utility [patent_app_number] => 15/716485 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716485 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716485
DDR memory bus with a reduced data strobe signal preamble timespan Sep 25, 2017 Issued
Array ( [id] => 14903735 [patent_doc_number] => 20190295633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => COMPLEMENTARY DUAL-MODULAR REDUNDANCY MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/317837 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16317837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/317837
Complementary dual-modular redundancy memory cell Sep 18, 2017 Issued
Array ( [id] => 16462888 [patent_doc_number] => 10846236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 15/702935 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 10337 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702935
Memory device and method of operating the same Sep 12, 2017 Issued
Array ( [id] => 13991901 [patent_doc_number] => 20190065108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => CORRECTING POWER LOSS IN NAND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 15/693121 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693121
Correcting power loss in NAND memory devices Aug 30, 2017 Issued
Array ( [id] => 14049307 [patent_doc_number] => 20190080760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => METHODS, COMPOSITIONS, AND DEVICES FOR INFORMATION STORAGE [patent_app_type] => utility [patent_app_number] => 15/690189 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690189
Methods, compositions, and devices for information storage Aug 28, 2017 Issued
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