Search

Mohammed A. Bashar

Examiner (ID: 5464, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
779
Issued Applications
680
Pending Applications
87
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12456636 [patent_doc_number] => 09984748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-29 [patent_title] => Electronic device and method for reading data stored in resistive memory cell [patent_app_type] => utility [patent_app_number] => 15/604474 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10933 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604474 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604474
Electronic device and method for reading data stored in resistive memory cell May 23, 2017 Issued
Array ( [id] => 13921077 [patent_doc_number] => 10204662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Stacked DRAM device and method of manufacture [patent_app_type] => utility [patent_app_number] => 15/603333 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603333 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603333
Stacked DRAM device and method of manufacture May 22, 2017 Issued
Array ( [id] => 15402459 [patent_doc_number] => 10541897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Mismatch compensation at differential signal receiver [patent_app_type] => utility [patent_app_number] => 15/596617 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 10798 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596617 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596617
Mismatch compensation at differential signal receiver May 15, 2017 Issued
Array ( [id] => 12053359 [patent_doc_number] => 20170329703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'SELF-MANAGEMENT MEMORY SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/595636 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15595636 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/595636
Self-management memory system and operating method thereof May 14, 2017 Issued
Array ( [id] => 14332535 [patent_doc_number] => 10297291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/590098 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 15746 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/590098
Semiconductor device May 8, 2017 Issued
Array ( [id] => 11939494 [patent_doc_number] => 20170243644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 15/589320 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589320
Refresh architecture and algorithm for non-volatile memories May 7, 2017 Issued
Array ( [id] => 11869289 [patent_doc_number] => 20170236574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/587656 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11729 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587656 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/587656
Semiconductor device May 4, 2017 Issued
Array ( [id] => 11838773 [patent_doc_number] => 20170220493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/489806 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5344 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489806 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489806
Semiconductor storage device and control method thereof Apr 17, 2017 Issued
Array ( [id] => 13159263 [patent_doc_number] => 10096365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Erasable block segmentation for memory [patent_app_type] => utility [patent_app_number] => 15/489276 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5744 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489276 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489276
Erasable block segmentation for memory Apr 16, 2017 Issued
Array ( [id] => 14457521 [patent_doc_number] => 10324721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Reducing aging of register file keeper circuits [patent_app_type] => utility [patent_app_number] => 15/488947 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 25869 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/488947
Reducing aging of register file keeper circuits Apr 16, 2017 Issued
Array ( [id] => 13482939 [patent_doc_number] => 20180293012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => System and Method for Cost and Power Optimized Heterogeneous Dual-Channel DDR DIMMs [patent_app_type] => utility [patent_app_number] => 15/484735 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484735 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/484735
System and method for cost and power optimized heterogeneous dual-channel DDR DIMMs Apr 10, 2017 Issued
Array ( [id] => 13891649 [patent_doc_number] => 10198372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Electronic device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/481308 [patent_app_country] => US [patent_app_date] => 2017-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 19326 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481308
Electronic device and method for fabricating the same Apr 5, 2017 Issued
Array ( [id] => 14220691 [patent_doc_number] => 20190122730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => Method and Means for Operating a Complementary Analogue Reconfigurable Memristive Resistive Switch and Use Thereof as an Artificial Synapse [patent_app_type] => utility [patent_app_number] => 16/092001 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16092001 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/092001
Method and means for operating a complementary analogue reconfigurable memristive resistive switch and use thereof as an artificial synapse Apr 2, 2017 Issued
Array ( [id] => 12249945 [patent_doc_number] => 09922727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Protection against state transition errors in solid-state data storage systems' [patent_app_type] => utility [patent_app_number] => 15/466004 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15466004 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/466004
Protection against state transition errors in solid-state data storage systems Mar 21, 2017 Issued
Array ( [id] => 13448685 [patent_doc_number] => 20180275885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/465751 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465751
Memory device Mar 21, 2017 Issued
Array ( [id] => 12571239 [patent_doc_number] => 10019332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-10 [patent_title] => Non-volatile memory with program failure recovery [patent_app_type] => utility [patent_app_number] => 15/456237 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 14724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15456237 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/456237
Non-volatile memory with program failure recovery Mar 9, 2017 Issued
Array ( [id] => 12243054 [patent_doc_number] => 20180075917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/445987 [patent_app_country] => US [patent_app_date] => 2017-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 26956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445987
Semiconductor memory device and memory system Feb 28, 2017 Issued
Array ( [id] => 14858701 [patent_doc_number] => 10418084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Pre-writing memory cells of an array [patent_app_type] => utility [patent_app_number] => 15/426871 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13975 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426871
Pre-writing memory cells of an array Feb 6, 2017 Issued
Array ( [id] => 13349143 [patent_doc_number] => 20180226111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => PROGRAMMABLE WRITE WORD LINE BOOST FOR LOW VOLTAGE MEMORY OPERATION [patent_app_type] => utility [patent_app_number] => 15/424418 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/424418
Programmable write word line boost for low voltage memory operation Feb 2, 2017 Issued
Array ( [id] => 13040867 [patent_doc_number] => 10042568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/417407 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 14068 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417407
Memory system and operating method thereof Jan 26, 2017 Issued
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