Search

Mohammed A. Bashar

Examiner (ID: 15502, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
757
Issued Applications
661
Pending Applications
87
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19546151 [patent_doc_number] => 20240363187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN [patent_app_type] => utility [patent_app_number] => 18/635569 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635569
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN Apr 14, 2024 Pending
Array ( [id] => 19546155 [patent_doc_number] => 20240363191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Usage-Based Disturbance Counter Repair [patent_app_type] => utility [patent_app_number] => 18/634096 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634096
Usage-Based Disturbance Counter Repair Apr 11, 2024 Pending
Array ( [id] => 19483752 [patent_doc_number] => 20240331794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => APPARATUSES AND METHODS FOR TESTING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/612284 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612284
APPARATUSES AND METHODS FOR TESTING MEMORY DEVICES Mar 20, 2024 Pending
Array ( [id] => 20596316 [patent_doc_number] => 12580039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Voting-based state selection for a volatile memory [patent_app_type] => utility [patent_app_number] => 18/611351 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611351
Voting-based state selection for a volatile memory Mar 19, 2024 Issued
Array ( [id] => 19285381 [patent_doc_number] => 20240221858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DYNAMIC ERROR MONITOR AND REPAIR [patent_app_type] => utility [patent_app_number] => 18/608220 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608220
Dynamic error monitor and repair Mar 17, 2024 Issued
Array ( [id] => 20002111 [patent_doc_number] => 20250140333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION [patent_app_type] => utility [patent_app_number] => 18/596939 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596939
SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION Mar 5, 2024 Pending
Array ( [id] => 19363919 [patent_doc_number] => 20240265953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE [patent_app_type] => utility [patent_app_number] => 18/581694 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581694 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581694
Area-efficient, width-adjustable signaling interface Feb 19, 2024 Issued
Array ( [id] => 20002112 [patent_doc_number] => 20250140334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR DEVICES RELATED TO PRECHARGE OPERATION [patent_app_type] => utility [patent_app_number] => 18/442866 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442866
SEMICONDUCTOR DEVICES RELATED TO PRECHARGE OPERATION Feb 14, 2024 Pending
Array ( [id] => 19384353 [patent_doc_number] => 20240274223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA [patent_app_type] => utility [patent_app_number] => 18/430406 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430406
APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA Jan 31, 2024 Pending
Array ( [id] => 19321195 [patent_doc_number] => 20240242741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => STACKED DRAM DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 18/420688 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420688
Stacked DRAM device and method of manufacture Jan 22, 2024 Issued
Array ( [id] => 20564861 [patent_doc_number] => 12567475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Pre-characterizing weak bits for increased low density parity check (LDPC) speed [patent_app_type] => utility [patent_app_number] => 18/415722 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415722 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415722
Pre-characterizing weak bits for increased low density parity check (LDPC) speed Jan 17, 2024 Issued
Array ( [id] => 19812193 [patent_doc_number] => 12243602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Method, device, and circuit for high-speed memories [patent_app_type] => utility [patent_app_number] => 18/411822 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411822
Method, device, and circuit for high-speed memories Jan 11, 2024 Issued
Array ( [id] => 20102893 [patent_doc_number] => 20250232829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => Data Storage Device and Method for Read Disturb Mitigation During Low-Power Modes [patent_app_type] => utility [patent_app_number] => 18/411397 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411397
Data storage device and method for read disturb mitigation during low-power modes Jan 11, 2024 Issued
Array ( [id] => 19305272 [patent_doc_number] => 20240233852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => BIT COUNTING CIRCUITS AND MEMORY DEVICES INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/406424 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406424
BIT COUNTING CIRCUITS AND MEMORY DEVICES INCLUDING THE SAME Jan 7, 2024 Pending
Array ( [id] => 20441335 [patent_doc_number] => 12512175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Non-volatile memory with enhanced early program termination mode for neighbor plane disturb [patent_app_type] => utility [patent_app_number] => 18/405156 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 17259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405156 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/405156
Non-volatile memory with enhanced early program termination mode for neighbor plane disturb Jan 4, 2024 Issued
Array ( [id] => 19634349 [patent_doc_number] => 20240412798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => Method for Scanning a Memory Array [patent_app_type] => utility [patent_app_number] => 18/403700 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403700
Method for Scanning a Memory Array Jan 2, 2024 Pending
Array ( [id] => 20636597 [patent_doc_number] => 12597478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/393544 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393544
Memory device Dec 20, 2023 Issued
Array ( [id] => 19812198 [patent_doc_number] => 12243607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Indicating a status of a memory built-in self-test [patent_app_type] => utility [patent_app_number] => 18/392487 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17944 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392487 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/392487
Indicating a status of a memory built-in self-test Dec 20, 2023 Issued
Array ( [id] => 20332571 [patent_doc_number] => 12462855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Data serializer, latch data device using the same and controlling method thereof [patent_app_type] => utility [patent_app_number] => 18/544612 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 1107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544612
Data serializer, latch data device using the same and controlling method thereof Dec 18, 2023 Issued
Array ( [id] => 19348932 [patent_doc_number] => 20240257896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MEMORY DEVICE INCLUDING REPAIR CIRCUIT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/543687 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543687
Memory device including repair circuit and operating method thereof Dec 17, 2023 Issued
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