Search

Mohammed A. Bashar

Examiner (ID: 5464, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
779
Issued Applications
680
Pending Applications
87
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11057082 [patent_doc_number] => 20160254044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/865754 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9724 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14865754 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/865754
Precharging and refreshing banks in memory device with bank group architecture Sep 24, 2015 Issued
Array ( [id] => 11050598 [patent_doc_number] => 20160247557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'BITLINE POSITIVE BOOST WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/862579 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12382 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862579 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862579
Bitline positive boost write-assist circuits for memory bit cells employing a P-type Field-Effect transistor (PFET) write port(s), and related systems and methods Sep 22, 2015 Issued
Array ( [id] => 11701519 [patent_doc_number] => 09691441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Memory programming methods and memory systems' [patent_app_type] => utility [patent_app_number] => 14/853557 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6277 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853557
Memory programming methods and memory systems Sep 13, 2015 Issued
Array ( [id] => 10794865 [patent_doc_number] => 20160141022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 14/830679 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7086 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830679 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830679
Apparatus for reducing write minimum supply voltage for memory Aug 18, 2015 Issued
Array ( [id] => 10681337 [patent_doc_number] => 20160027482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'Communication Interface Architecture Using Serializer/Deserializer' [patent_app_type] => utility [patent_app_number] => 14/810261 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810261 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810261
Communication interface architecture using serializer/deserializer Jul 26, 2015 Issued
Array ( [id] => 11246229 [patent_doc_number] => 09472274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-18 [patent_title] => 'Refresh of nonvolatile memory cells and reference cells with resistance drift' [patent_app_type] => utility [patent_app_number] => 14/788969 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9726 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788969 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/788969
Refresh of nonvolatile memory cells and reference cells with resistance drift Jun 30, 2015 Issued
Array ( [id] => 10417913 [patent_doc_number] => 20150302924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/753938 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14753938 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/753938
Refresh architecture and algorithm for non-volatile memories Jun 28, 2015 Issued
Array ( [id] => 10747251 [patent_doc_number] => 20160093401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'INTEGRATED CIRCUITS WITH BUILT-IN SELF TEST MECHANISM' [patent_app_type] => utility [patent_app_number] => 14/750102 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4916 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750102
Integrated circuits with built-in self test mechanism Jun 24, 2015 Issued
Array ( [id] => 12759745 [patent_doc_number] => 20180145083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => CONTROLLED MODIFICATION OF ANTIFUSE PROGRAMMING VOLTAGE [patent_app_type] => utility [patent_app_number] => 15/575792 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15575792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/575792
CONTROLLED MODIFICATION OF ANTIFUSE PROGRAMMING VOLTAGE Jun 24, 2015 Abandoned
Array ( [id] => 11353430 [patent_doc_number] => 20160372170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'APPARATUSES AND METHODS FOR CHIP IDENTIFICATION IN A MEMORY PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/746435 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6989 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14746435 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/746435
Apparatuses and methods for chip identification in a memory package Jun 21, 2015 Issued
Array ( [id] => 10771958 [patent_doc_number] => 20160118114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/743488 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/743488
Resistive memory device, resistive memory system and method of operating the resistive memory device Jun 17, 2015 Issued
Array ( [id] => 11096265 [patent_doc_number] => 20160293234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'PIPELINING AN ASYNCHRONOUS MEMORY REUSING A SENSE AMP AND AN OUTPUT LATCH' [patent_app_type] => utility [patent_app_number] => 14/742706 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742706 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742706
Pipelining an asynchronous memory reusing a sense amp and an output latch Jun 17, 2015 Issued
Array ( [id] => 11577606 [patent_doc_number] => 09632868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Storage device including nonvolatile memory and memory controller and operating method of storage device' [patent_app_type] => utility [patent_app_number] => 14/743279 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 16951 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/743279
Storage device including nonvolatile memory and memory controller and operating method of storage device Jun 17, 2015 Issued
Array ( [id] => 10703034 [patent_doc_number] => 20160049180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING INPUT/OUTPUT CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/726063 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726063 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726063
Semiconductor device including input/output circuit May 28, 2015 Issued
Array ( [id] => 11079368 [patent_doc_number] => 20160276331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'STRAPPING STRUCTURE OF MEMORY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/723615 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723615
Strapping structure of memory circuit May 27, 2015 Issued
Array ( [id] => 10666741 [patent_doc_number] => 20160012886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'NON-VOLATILE MEMORY CELL UTILIZING VOLATILE SWITCHING TWO TERMINAL DEVICE AND A MOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/717185 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15400 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14717185 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/717185
Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor May 19, 2015 Issued
Array ( [id] => 11125134 [patent_doc_number] => 20160322108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'Use of Dummy Word Lines for Metadata Storage' [patent_app_type] => utility [patent_app_number] => 14/700500 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8493 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700500
Use of dummy word lines for metadata storage Apr 29, 2015 Issued
Array ( [id] => 10440271 [patent_doc_number] => 20150325283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/685491 [patent_app_country] => US [patent_app_date] => 2015-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11722 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14685491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/685491
Semiconductor device Apr 12, 2015 Issued
Array ( [id] => 11599535 [patent_doc_number] => 09646711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 14/676819 [patent_app_country] => US [patent_app_date] => 2015-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 75 [patent_no_of_words] => 23501 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676819 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676819
Memory device Apr 1, 2015 Issued
Array ( [id] => 10794856 [patent_doc_number] => 20160141013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'MANAGING SKEW IN DATA SIGNALS WITH ADJUSTABLE STROBE' [patent_app_type] => utility [patent_app_number] => 14/672787 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9566 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672787
Managing skew in data signals with adjustable strobe Mar 29, 2015 Issued
Menu