Search

Mohammed A. Bashar

Examiner (ID: 5464, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
779
Issued Applications
680
Pending Applications
87
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9939121 [patent_doc_number] => 08988940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Structure and method for narrowing voltage threshold distribution in non-volatile memories' [patent_app_type] => utility [patent_app_number] => 13/562667 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6887 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562667
Structure and method for narrowing voltage threshold distribution in non-volatile memories Jul 30, 2012 Issued
Array ( [id] => 8827631 [patent_doc_number] => 20130128675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM AND CONTROLLER OPERATING METHOD' [patent_app_type] => utility [patent_app_number] => 13/562373 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562373 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562373
Nonvolatile memory device, memory system and controller operating method Jul 30, 2012 Issued
Array ( [id] => 9279365 [patent_doc_number] => 20140029333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'FIVE TRANSISTOR SRAM CELL' [patent_app_type] => utility [patent_app_number] => 13/561469 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6986 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561469 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/561469
Five transistor SRAM cell Jul 29, 2012 Issued
Array ( [id] => 9279397 [patent_doc_number] => 20140029365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'PRECHARGE OPERATIONS AND CIRCUITRY THERE FOR' [patent_app_type] => utility [patent_app_number] => 13/560181 [patent_app_country] => US [patent_app_date] => 2012-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13560181 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/560181
Appatuses and methods for precharge operations and accumulated charge dissipation Jul 26, 2012 Issued
Array ( [id] => 8902804 [patent_doc_number] => 20130170307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR TESTING ENDURANCE OF MEMORY' [patent_app_type] => utility [patent_app_number] => 13/559567 [patent_app_country] => US [patent_app_date] => 2012-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1414 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13559567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/559567
ELECTRONIC DEVICE AND METHOD FOR TESTING ENDURANCE OF MEMORY Jul 25, 2012 Abandoned
Array ( [id] => 10106532 [patent_doc_number] => 09142315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Methods and systems for adjusting NVM cell bias conditions for read/verify operations to compensate for performance degradation' [patent_app_type] => utility [patent_app_number] => 13/557449 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7028 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557449 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/557449
Methods and systems for adjusting NVM cell bias conditions for read/verify operations to compensate for performance degradation Jul 24, 2012 Issued
Array ( [id] => 8636209 [patent_doc_number] => 20130028012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/556431 [patent_app_country] => US [patent_app_date] => 2012-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6014 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13556431 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/556431
Semiconductor integrated circuit and processor Jul 23, 2012 Issued
Array ( [id] => 10066460 [patent_doc_number] => 09105315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Controlling the voltage level on the word line to maintain performance and reduce access disturbs' [patent_app_type] => utility [patent_app_number] => 13/555255 [patent_app_country] => US [patent_app_date] => 2012-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13555255 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/555255
Controlling the voltage level on the word line to maintain performance and reduce access disturbs Jul 22, 2012 Issued
Array ( [id] => 8840318 [patent_doc_number] => 20130135946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'DUAL RAIL MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/551387 [patent_app_country] => US [patent_app_date] => 2012-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551387 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/551387
Dual rail memory architecture Jul 16, 2012 Issued
Array ( [id] => 10003849 [patent_doc_number] => 09047948 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-02 [patent_title] => 'Programmable window of operation for CBRAM' [patent_app_type] => utility [patent_app_number] => 13/548429 [patent_app_country] => US [patent_app_date] => 2012-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10471 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548429 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/548429
Programmable window of operation for CBRAM Jul 12, 2012 Issued
Array ( [id] => 8611247 [patent_doc_number] => 20130016559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'NAND FLASH MEMORY SYSTEM AND METHOD PROVIDING REDUCED POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 13/547435 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547435 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/547435
NAND FLASH MEMORY SYSTEM AND METHOD PROVIDING REDUCED POWER CONSUMPTION Jul 11, 2012 Abandoned
Array ( [id] => 9221618 [patent_doc_number] => 20140016393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'Memory Programming Methods And Memory Systems' [patent_app_type] => utility [patent_app_number] => 13/546919 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6227 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546919 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/546919
Memory programming methods and memory systems Jul 10, 2012 Issued
Array ( [id] => 10010296 [patent_doc_number] => 09053819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Programming method to tighten threshold voltage width with avoiding program disturb' [patent_app_type] => utility [patent_app_number] => 13/546553 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 16231 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546553 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/546553
Programming method to tighten threshold voltage width with avoiding program disturb Jul 10, 2012 Issued
Array ( [id] => 10852624 [patent_doc_number] => 08879318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Method of storing data in nonvolatile memory device and method of operating nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/545127 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 14707 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/545127
Method of storing data in nonvolatile memory device and method of operating nonvolatile memory device Jul 9, 2012 Issued
Array ( [id] => 8864733 [patent_doc_number] => 20130148436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTIVALUED DATA' [patent_app_type] => utility [patent_app_number] => 13/544147 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 17959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544147 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/544147
SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTIVALUED DATA Jul 8, 2012 Abandoned
Array ( [id] => 9203975 [patent_doc_number] => 20140003152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'METHODS FOR EXTENDING THE EFFECTIVE VOLTAGE WINDOW OF A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/540351 [patent_app_country] => US [patent_app_date] => 2012-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14766 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13540351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/540351
Methods for extending the effective voltage window of a memory cell Jul 1, 2012 Issued
Array ( [id] => 9203958 [patent_doc_number] => 20140003135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SRAM BITCELL IMPLEMENTED IN DOUBLE GATE TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 13/539577 [patent_app_country] => US [patent_app_date] => 2012-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10131 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539577 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/539577
SRAM bitcell implemented in double gate technology Jul 1, 2012 Issued
Array ( [id] => 10028518 [patent_doc_number] => 09070424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Sense amplifier circuitry for resistive type memory' [patent_app_type] => utility [patent_app_number] => 13/538869 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 12496 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538869
Sense amplifier circuitry for resistive type memory Jun 28, 2012 Issued
Array ( [id] => 9204373 [patent_doc_number] => 20140003550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'DUTY CYCLE COMPENSATION OF RAM TRANSMITTERS' [patent_app_type] => utility [patent_app_number] => 13/536567 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8308 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13536567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/536567
Duty cycle compensation of RAM transmitters Jun 27, 2012 Issued
Array ( [id] => 8706729 [patent_doc_number] => 20130064018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'MEMORY ACCESS CIRCUIT FOR DOUBLE DATA/SINGLE DATA RATE APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 13/535381 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5012 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535381 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535381
Memory access circuit for double data/single data rate applications Jun 27, 2012 Issued
Menu