Mohammed A. Bashar

Array ( [id] => 19384352 [patent_doc_number] => 20240274222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => TECHNIQUE TO ANALYZE AND REPORT ACCURATE DATA, SYNCHRONIZING MULTIPLE SIGNALS IN A MEMORY CHIP [patent_app_type] => utility [patent_app_number] => 18/534495 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20002113 [patent_doc_number] => 20250140335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SYSTEM AND METHOD FOR TESTING MEMORY [patent_app_type] => utility [patent_app_number] => 18/496427 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18496427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18974974 [patent_doc_number] => 20240055066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO [patent_app_type] => utility [patent_app_number] => 18/486789 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19252523 [patent_doc_number] => 20240203520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS [patent_app_type] => utility [patent_app_number] => 18/485631 [patent_app_country] => US [patent_app_date] => 2023-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19483748 [patent_doc_number] => 20240331790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => STORAGE DEVICE FOR SUPPORTING DYNAMIC ALLOCATION OF MEMORY AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/482464 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18905037 [patent_doc_number] => 20240020522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => PERFORMANCE AND AREA EFFICIENT SYNAPSE MEMORY CELL STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/475767 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19850414 [patent_doc_number] => 20250095765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => ERROR CONDITION MONITORING IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/369014 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18882642 [patent_doc_number] => 20240006011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SYSTEMS AND METHODS FOR MONITORING AND MANAGING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/467996 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20581213 [patent_doc_number] => 12573467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Sense amplifier and output latch circuit for testing [patent_app_type] => utility [patent_app_number] => 18/463905 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19835510 [patent_doc_number] => 20250087296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => Row Repair Circuitry [patent_app_type] => utility [patent_app_number] => 18/243441 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19384342 [patent_doc_number] => 20240274212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/241621 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18241621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20266826 [patent_doc_number] => 12437822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory device and reading method thereof [patent_app_type] => utility [patent_app_number] => 18/458201 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19926061 [patent_doc_number] => 12300353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Memory device and memory system [patent_app_type] => utility [patent_app_number] => 18/238232 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5944 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18833594 [patent_doc_number] => 20230402121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD FOR OPTIMIZING FLASH MEMORY CHIP AND RELATED APPARATUS [patent_app_type] => utility [patent_app_number] => 18/455031 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20111299 [patent_doc_number] => 12362034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor device related to a parallel test [patent_app_type] => utility [patent_app_number] => 18/453903 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18833597 [patent_doc_number] => 20230402124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SYSTEM AND METHOD FOR PARALLEL MEMORY TEST [patent_app_type] => utility [patent_app_number] => 18/453400 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19146005 [patent_doc_number] => 20240145021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => FLASH MEMORY FOR PERFORMING MARGIN READ TEST OPERATION AND MARGIN READ TEST SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/236177 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18812244 [patent_doc_number] => 20230386581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Non-Volatile Memory Device and Method of Operating the Same [patent_app_type] => utility [patent_app_number] => 18/450241 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19285383 [patent_doc_number] => 20240221860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/448346 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19661809 [patent_doc_number] => 20240428874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => ABORTED OPERATION DETECTION FOR NONVOLATILE MEMORY WITH NON-UNIFORM ERASE [patent_app_type] => utility [patent_app_number] => 18/366213 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366213 [rel_patent_id] =>[rel_patent_doc_number] =>)