Search

Mohammed A. Bashar

Examiner (ID: 5613, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
739
Issued Applications
646
Pending Applications
94
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19687742 [patent_doc_number] => 20250006287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NON-VOLATILE MEMORY WITH LAYOUT ADAPTIVE PROBLEMATIC WORD LINE DETECTION [patent_app_type] => utility [patent_app_number] => 18/346367 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346367
Non-volatile memory with layout adaptive problematic word line detection Jul 2, 2023 Issued
Array ( [id] => 19687745 [patent_doc_number] => 20250006290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING [patent_app_type] => utility [patent_app_number] => 18/343377 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343377
HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING Jun 27, 2023 Pending
Array ( [id] => 19687745 [patent_doc_number] => 20250006290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING [patent_app_type] => utility [patent_app_number] => 18/343377 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343377
HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING Jun 27, 2023 Pending
Array ( [id] => 20118229 [patent_doc_number] => 12367944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Memory device including test pad connection circuit [patent_app_type] => utility [patent_app_number] => 18/341192 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 5856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/341192
Memory device including test pad connection circuit Jun 25, 2023 Issued
Array ( [id] => 19634348 [patent_doc_number] => 20240412797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => Fully Scannable Memory Arrays [patent_app_type] => utility [patent_app_number] => 18/207482 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207482
Fully Scannable Memory Arrays Jun 7, 2023 Pending
Array ( [id] => 19589381 [patent_doc_number] => 20240386938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHODS FOR CONTROLLING BIT LINE VOLTAGES IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/328186 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328186
METHODS FOR CONTROLLING BIT LINE VOLTAGES IN MEMORY DEVICES Jun 1, 2023 Pending
Array ( [id] => 19237050 [patent_doc_number] => 20240194245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/325109 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325109
Storage device and operating method thereof May 29, 2023 Issued
Array ( [id] => 19237050 [patent_doc_number] => 20240194245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/325109 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325109
Storage device and operating method thereof May 29, 2023 Issued
Array ( [id] => 20345822 [patent_doc_number] => 12469557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Semiconductor device and operating method for controlling driving direction of word line [patent_app_type] => utility [patent_app_number] => 18/323950 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4501 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323950
Semiconductor device and operating method for controlling driving direction of word line May 24, 2023 Issued
Array ( [id] => 20229161 [patent_doc_number] => 12417815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Memory device including error correction device [patent_app_type] => utility [patent_app_number] => 18/314147 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9357 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314147
Memory device including error correction device May 8, 2023 Issued
Array ( [id] => 18599987 [patent_doc_number] => 20230274788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => METHOD AND SYSTEM FOR REPLACEMENT OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/314743 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314743
Method and system for replacement of memory cells May 8, 2023 Issued
Array ( [id] => 20229161 [patent_doc_number] => 12417815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Memory device including error correction device [patent_app_type] => utility [patent_app_number] => 18/314147 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9357 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314147
Memory device including error correction device May 8, 2023 Issued
Array ( [id] => 18555046 [patent_doc_number] => 20230253062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => BUILT-IN MEMORY REPAIR WITH REPAIR CODE COMPRESSION [patent_app_type] => utility [patent_app_number] => 18/301327 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301327
Built-in memory repair with repair code compression Apr 16, 2023 Issued
Array ( [id] => 18789056 [patent_doc_number] => 20230377669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY DEVICES, OPERATING METHODS OF THE MEMORY DEVICES, AND TEST SYSTEMS INCLUDING THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/134776 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134776
Memory devices, operating methods of the memory devices, and test systems including the memory devices Apr 13, 2023 Issued
Array ( [id] => 18789056 [patent_doc_number] => 20230377669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY DEVICES, OPERATING METHODS OF THE MEMORY DEVICES, AND TEST SYSTEMS INCLUDING THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/134776 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134776
Memory devices, operating methods of the memory devices, and test systems including the memory devices Apr 13, 2023 Issued
Array ( [id] => 18789056 [patent_doc_number] => 20230377669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY DEVICES, OPERATING METHODS OF THE MEMORY DEVICES, AND TEST SYSTEMS INCLUDING THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/134776 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134776
Memory devices, operating methods of the memory devices, and test systems including the memory devices Apr 13, 2023 Issued
Array ( [id] => 19435761 [patent_doc_number] => 20240304259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => VOLTAGE PREDICTION METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/298335 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/298335
Voltage prediction method, memory storage device and memory control circuit unit Apr 9, 2023 Issued
Array ( [id] => 19435748 [patent_doc_number] => 20240304246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => METHOD AND SYSTEM FOR ADJUSTABLE TOP SELECT GATE CONTROL [patent_app_type] => utility [patent_app_number] => 18/124946 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124946
METHOD AND SYSTEM FOR ADJUSTABLE TOP SELECT GATE CONTROL Mar 21, 2023 Pending
Array ( [id] => 18514372 [patent_doc_number] => 20230230627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE MANAGING FLEXIBLE REFRESH SKIP AREA [patent_app_type] => utility [patent_app_number] => 18/125098 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18125098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/125098
Semiconductor memory device managing flexible refresh skip area Mar 21, 2023 Issued
Array ( [id] => 19435748 [patent_doc_number] => 20240304246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => METHOD AND SYSTEM FOR ADJUSTABLE TOP SELECT GATE CONTROL [patent_app_type] => utility [patent_app_number] => 18/124946 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124946
METHOD AND SYSTEM FOR ADJUSTABLE TOP SELECT GATE CONTROL Mar 21, 2023 Pending
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