Search

Mohammed A. Bashar

Examiner (ID: 15502, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
757
Issued Applications
661
Pending Applications
87
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18553782 [patent_doc_number] => 20230251794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => BUFFER CIRCUIT WITH DATA BIT INVERSION [patent_app_type] => utility [patent_app_number] => 18/093258 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093258
Buffer circuit with data bit inversion Jan 3, 2023 Issued
Array ( [id] => 19827902 [patent_doc_number] => 12248684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Non-volatile memory device optimized for a surface mount technology (SMT) process and an operating method thereof [patent_app_type] => utility [patent_app_number] => 18/090658 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 17583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090658 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090658
Non-volatile memory device optimized for a surface mount technology (SMT) process and an operating method thereof Dec 28, 2022 Issued
Array ( [id] => 18540589 [patent_doc_number] => 20230245699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SENSE AMPLIFIER ARCHITECTURE FOR A NON-VOLATILE MEMORY STORING CODED INFORMATION [patent_app_type] => utility [patent_app_number] => 18/148380 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148380
Sense amplifier architecture for a non-volatile memory storing coded information Dec 28, 2022 Issued
Array ( [id] => 20266828 [patent_doc_number] => 12437824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Configuration method and reading method of 3D memory device, 3D memory device, and memory system [patent_app_type] => utility [patent_app_number] => 18/090423 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090423
Configuration method and reading method of 3D memory device, 3D memory device, and memory system Dec 27, 2022 Issued
Array ( [id] => 18471426 [patent_doc_number] => 20230205712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => MEMORY DEVICES WITH MULTIPLE PSEUDO-CHANNELS [patent_app_type] => utility [patent_app_number] => 18/084452 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084452 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084452
MEMORY DEVICES WITH MULTIPLE PSEUDO-CHANNELS Dec 18, 2022 Pending
Array ( [id] => 18925214 [patent_doc_number] => 20240028218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/076029 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/076029
Memory device and method of operating the same Dec 5, 2022 Issued
Array ( [id] => 19223751 [patent_doc_number] => 20240188455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => PROXIMITY HEATER TO LOWER RRAM FORMING VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/061312 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061312
Proximity heater to lower RRAM forming voltage Dec 1, 2022 Issued
Array ( [id] => 18599981 [patent_doc_number] => 20230274782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => METHOD FOR ERASING FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 18/072723 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072723 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/072723
Method for erasing flash memory Nov 30, 2022 Issued
Array ( [id] => 19022880 [patent_doc_number] => 20240079051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/983331 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983331 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983331
Memory cell Nov 7, 2022 Issued
Array ( [id] => 18669737 [patent_doc_number] => 11776647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory repair using optimized redundancy utilization [patent_app_type] => utility [patent_app_number] => 17/982512 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982512 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982512
Memory repair using optimized redundancy utilization Nov 6, 2022 Issued
Array ( [id] => 18213657 [patent_doc_number] => 20230059923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => EXECUTING A REFRESH OPERATION IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/980234 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980234
Executing a refresh operation in a memory sub-system Nov 2, 2022 Issued
Array ( [id] => 19596791 [patent_doc_number] => 12154644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Test device and test method thereof [patent_app_type] => utility [patent_app_number] => 17/978199 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2936 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17978199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/978199
Test device and test method thereof Oct 30, 2022 Issued
Array ( [id] => 18167263 [patent_doc_number] => 20230033870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => MEMORY DEVICE VIRTUAL BLOCKS USING HALF GOOD BLOCKS [patent_app_type] => utility [patent_app_number] => 17/965481 [patent_app_country] => US [patent_app_date] => 2022-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/965481
Memory device virtual blocks using half good blocks Oct 12, 2022 Issued
Array ( [id] => 18294527 [patent_doc_number] => 20230104213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => Electronic Circuit and Method of Operating an Electronic Circuit [patent_app_type] => utility [patent_app_number] => 17/961181 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961181
Electronic Circuit and Method of Operating an Electronic Circuit Oct 5, 2022 Pending
Array ( [id] => 18514385 [patent_doc_number] => 20230230640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => NONVOLATILE MEMORY DEVICE INCLUDING COMBINED SENSING NODE AND CACHE READ METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/960630 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17960630 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/960630
Nonvolatile memory device including combined sensing node and cache read method thereof Oct 4, 2022 Issued
Array ( [id] => 20332591 [patent_doc_number] => 12462875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Program scheme for edge data wordlines in a memory device [patent_app_type] => utility [patent_app_number] => 17/959171 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959171
Program scheme for edge data wordlines in a memory device Oct 2, 2022 Issued
Array ( [id] => 19782082 [patent_doc_number] => 12231129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Signal generator and memory [patent_app_type] => utility [patent_app_number] => 17/937404 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8419 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937404
Signal generator and memory Sep 29, 2022 Issued
Array ( [id] => 19168266 [patent_doc_number] => 11984177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Memory component provided with a test interface [patent_app_type] => utility [patent_app_number] => 17/957274 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6041 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957274
Memory component provided with a test interface Sep 29, 2022 Issued
Array ( [id] => 19085924 [patent_doc_number] => 20240112725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SEMICONDUCTOR DEVICE HAVING READ DATA BUSES AND WRITE DATA BUSES [patent_app_type] => utility [patent_app_number] => 17/936785 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936785
Semiconductor device having read data buses and write data buses Sep 28, 2022 Issued
Array ( [id] => 18848485 [patent_doc_number] => 20230410889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/954336 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954336
Semiconductor device and memory Sep 27, 2022 Issued
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