
Mohammed A. Bashar
Examiner (ID: 13174, Phone: (571)272-2908 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 746 |
| Issued Applications | 652 |
| Pending Applications | 90 |
| Abandoned Applications | 33 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18898331
[patent_doc_number] => 20240013816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => CIRCUIT FOR TRACKING ACCESS OCCURRENCES
[patent_app_type] => utility
[patent_app_number] => 17/811794
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13060
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811794
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/811794 | Circuit for tracking access occurrences | Jul 10, 2022 | Issued |
Array
(
[id] => 17949018
[patent_doc_number] => 20220336037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => DYNAMIC ERROR MONITOR AND REPAIR
[patent_app_type] => utility
[patent_app_number] => 17/856756
[patent_app_country] => US
[patent_app_date] => 2022-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7728
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856756
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/856756 | Dynamic error monitor and repair | Jun 30, 2022 | Issued |
Array
(
[id] => 18882643
[patent_doc_number] => 20240006012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => VIRTUALIZED SCAN CHAIN TESTING IN A RANDOM ACCESS MEMORY (RAM) ARRAY
[patent_app_type] => utility
[patent_app_number] => 17/856262
[patent_app_country] => US
[patent_app_date] => 2022-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20663
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856262
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/856262 | Virtualized scan chain testing in a random access memory (RAM) array | Jun 30, 2022 | Issued |
Array
(
[id] => 19925087
[patent_doc_number] => 12299371
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Dummy cells placed adjacent functional blocks
[patent_app_type] => utility
[patent_app_number] => 17/852985
[patent_app_country] => US
[patent_app_date] => 2022-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 6923
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852985
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/852985 | Dummy cells placed adjacent functional blocks | Jun 28, 2022 | Issued |
Array
(
[id] => 19487098
[patent_doc_number] => 12106822
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Memory array with programmable number of filters
[patent_app_type] => utility
[patent_app_number] => 17/852193
[patent_app_country] => US
[patent_app_date] => 2022-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 7470
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852193
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/852193 | Memory array with programmable number of filters | Jun 27, 2022 | Issued |
Array
(
[id] => 19796027
[patent_doc_number] => 12236992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-25
[patent_title] => Refresh determination using memory cell patterns
[patent_app_type] => utility
[patent_app_number] => 17/852221
[patent_app_country] => US
[patent_app_date] => 2022-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7852
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852221
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/852221 | Refresh determination using memory cell patterns | Jun 27, 2022 | Issued |
Array
(
[id] => 18528544
[patent_doc_number] => 11715542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-01
[patent_title] => Semiconductor device including defect detection circuit and method of detecting defects in the same
[patent_app_type] => utility
[patent_app_number] => 17/851596
[patent_app_country] => US
[patent_app_date] => 2022-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
[patent_no_of_words] => 13262
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851596
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/851596 | Semiconductor device including defect detection circuit and method of detecting defects in the same | Jun 27, 2022 | Issued |
Array
(
[id] => 18669740
[patent_doc_number] => 11776650
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => Memory calibration device, system and method
[patent_app_type] => utility
[patent_app_number] => 17/846578
[patent_app_country] => US
[patent_app_date] => 2022-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 23766
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846578
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/846578 | Memory calibration device, system and method | Jun 21, 2022 | Issued |
Array
(
[id] => 18848529
[patent_doc_number] => 20230410933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST
[patent_app_type] => utility
[patent_app_number] => 17/807625
[patent_app_country] => US
[patent_app_date] => 2022-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807625
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/807625 | Indicating a status of a memory built-in self-test | Jun 16, 2022 | Issued |
Array
(
[id] => 19260676
[patent_doc_number] => 12020741
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-25
[patent_title] => Managing data refresh in semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/838921
[patent_app_country] => US
[patent_app_date] => 2022-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 14062
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838921
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/838921 | Managing data refresh in semiconductor devices | Jun 12, 2022 | Issued |
Array
(
[id] => 19356716
[patent_doc_number] => 12057171
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-06
[patent_title] => Method of improving endurance of nor flash
[patent_app_type] => utility
[patent_app_number] => 17/834912
[patent_app_country] => US
[patent_app_date] => 2022-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1825
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834912
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/834912 | Method of improving endurance of nor flash | Jun 6, 2022 | Issued |
Array
(
[id] => 18532998
[patent_doc_number] => 20230238073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-27
[patent_title] => METHOD, DEVICE, AND CIRCUIT FOR HIGH-SPEED MEMORIES
[patent_app_type] => utility
[patent_app_number] => 17/834122
[patent_app_country] => US
[patent_app_date] => 2022-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6129
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834122
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/834122 | Method, device, and circuit for high-speed memories | Jun 6, 2022 | Issued |
Array
(
[id] => 18562752
[patent_doc_number] => 11728002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-15
[patent_title] => Memory device with analog measurement mode features
[patent_app_type] => utility
[patent_app_number] => 17/826423
[patent_app_country] => US
[patent_app_date] => 2022-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5794
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826423
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/826423 | Memory device with analog measurement mode features | May 26, 2022 | Issued |
Array
(
[id] => 18812231
[patent_doc_number] => 20230386568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/825048
[patent_app_country] => US
[patent_app_date] => 2022-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14575
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825048
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/825048 | High speed multi-level cell (MLC) programming in non-volatile memory structures | May 25, 2022 | Issued |
Array
(
[id] => 18488136
[patent_doc_number] => 20230215484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/824634
[patent_app_country] => US
[patent_app_date] => 2022-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10965
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824634
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/824634 | Semiconductor memory device and operating method thereof | May 24, 2022 | Issued |
Array
(
[id] => 18874456
[patent_doc_number] => 11862277
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-02
[patent_title] => Deterioration detection device
[patent_app_type] => utility
[patent_app_number] => 17/750317
[patent_app_country] => US
[patent_app_date] => 2022-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8978
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750317
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/750317 | Deterioration detection device | May 20, 2022 | Issued |
Array
(
[id] => 18464191
[patent_doc_number] => 11688484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Debugging memory devices
[patent_app_type] => utility
[patent_app_number] => 17/748959
[patent_app_country] => US
[patent_app_date] => 2022-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 18396
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748959
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/748959 | Debugging memory devices | May 18, 2022 | Issued |
Array
(
[id] => 19198906
[patent_doc_number] => 11996154
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-28
[patent_title] => Page buffer circuit and nonvolatile memory device including the same
[patent_app_type] => utility
[patent_app_number] => 17/745594
[patent_app_country] => US
[patent_app_date] => 2022-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 10854
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745594
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/745594 | Page buffer circuit and nonvolatile memory device including the same | May 15, 2022 | Issued |
Array
(
[id] => 19341281
[patent_doc_number] => 12051476
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Testing disruptive memories
[patent_app_type] => utility
[patent_app_number] => 17/662862
[patent_app_country] => US
[patent_app_date] => 2022-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9113
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662862
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/662862 | Testing disruptive memories | May 10, 2022 | Issued |
Array
(
[id] => 19488846
[patent_doc_number] => 12108589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Memory device through use of semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/741914
[patent_app_country] => US
[patent_app_date] => 2022-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 38
[patent_no_of_words] => 13065
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 392
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741914
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/741914 | Memory device through use of semiconductor device | May 10, 2022 | Issued |