Search

Mohammed A. Bashar

Examiner (ID: 13174, Phone: (571)272-2908 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
746
Issued Applications
652
Pending Applications
90
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18446893 [patent_doc_number] => 11682468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Method and system for replacement of memory cells [patent_app_type] => utility [patent_app_number] => 17/740302 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/740302
Method and system for replacement of memory cells May 8, 2022 Issued
Array ( [id] => 18255176 [patent_doc_number] => 20230082215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => INTEGRATED CIRCUIT DEVICE INCLUDING AN SRAM PORTION HAVING END POWER SELECT CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/738306 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738306
Integrated circuit device including an SRAM portion having end power select circuits May 5, 2022 Issued
Array ( [id] => 19459952 [patent_doc_number] => 12100454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Memory device including in-tier driver circuit [patent_app_type] => utility [patent_app_number] => 17/734623 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 68 [patent_no_of_words] => 18717 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734623
Memory device including in-tier driver circuit May 1, 2022 Issued
Array ( [id] => 18307567 [patent_doc_number] => 20230111467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/731994 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731994
Semiconductor memory device and method of operating semiconductor memory device Apr 27, 2022 Issued
Array ( [id] => 18394585 [patent_doc_number] => 20230162806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => APPARATUS AND METHOD FOR REDUCING SIGNAL INTERFERENCE IN A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/730917 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730917
Apparatus and method for reducing signal interference in a semiconductor device Apr 26, 2022 Issued
Array ( [id] => 19567557 [patent_doc_number] => 12142334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Health scan for content addressable memory [patent_app_type] => utility [patent_app_number] => 17/729973 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729973
Health scan for content addressable memory Apr 25, 2022 Issued
Array ( [id] => 18039740 [patent_doc_number] => 20220383957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => NONVOLATILE MEMORY WRITING DEVICE [patent_app_type] => utility [patent_app_number] => 17/728229 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728229
Nonvolatile memory writing device Apr 24, 2022 Issued
Array ( [id] => 19733573 [patent_doc_number] => 12211573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Burst indicator systems and methods [patent_app_type] => utility [patent_app_number] => 17/725025 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 12813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725025
Burst indicator systems and methods Apr 19, 2022 Issued
Array ( [id] => 18712532 [patent_doc_number] => 20230335165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => STANDBY EXIT FOR MEMORY DIE STACK [patent_app_type] => utility [patent_app_number] => 17/723798 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723798 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723798
Standby exit for memory die stack Apr 18, 2022 Issued
Array ( [id] => 18712559 [patent_doc_number] => 20230335192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DIVIDED CLOCK TRANSMISSION IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/723673 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723673
Divided clock transmission in a three-dimensional stacked memory device Apr 18, 2022 Issued
Array ( [id] => 18874455 [patent_doc_number] => 11862276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Memory test method and memory test apparatus [patent_app_type] => utility [patent_app_number] => 17/659336 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3833 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659336
Memory test method and memory test apparatus Apr 14, 2022 Issued
Array ( [id] => 18696109 [patent_doc_number] => 20230326540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => TEST CIRCUIT IN SCRIBE REGION FOR MEMORY FAILURE ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/719327 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/719327
Test circuit in scribe region for memory failure analysis Apr 11, 2022 Issued
Array ( [id] => 18890840 [patent_doc_number] => 11869617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Self-repair for sequential SRAM [patent_app_type] => utility [patent_app_number] => 17/658740 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11666 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658740
Self-repair for sequential SRAM Apr 10, 2022 Issued
Array ( [id] => 18500308 [patent_doc_number] => 20230223093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => METHOD FOR GENERATING AN MEMORY BUILT-IN SELF-TEST ALGORITHM CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/717928 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717928 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/717928
Method for generating an memory built-in self-test algorithm circuit Apr 10, 2022 Issued
Array ( [id] => 19029745 [patent_doc_number] => 11929108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Memory detection method, computer device and storage medium [patent_app_type] => utility [patent_app_number] => 17/700871 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5961 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700871
Memory detection method, computer device and storage medium Mar 21, 2022 Issued
Array ( [id] => 18661058 [patent_doc_number] => 20230307071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => VERIFY TECHNIQUES FOR CURRENT REDUCTION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/701320 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701320
Verify techniques for current reduction in a memory device Mar 21, 2022 Issued
Array ( [id] => 19951069 [patent_doc_number] => 12322439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Neuromorphic memory circuit and operating method therof [patent_app_type] => utility [patent_app_number] => 17/699756 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699756 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699756
Neuromorphic memory circuit and operating method therof Mar 20, 2022 Issued
Array ( [id] => 18593132 [patent_doc_number] => 11742041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks [patent_app_type] => utility [patent_app_number] => 17/655447 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655447
Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks Mar 17, 2022 Issued
Array ( [id] => 18593132 [patent_doc_number] => 11742041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks [patent_app_type] => utility [patent_app_number] => 17/655447 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655447
Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks Mar 17, 2022 Issued
Array ( [id] => 18593132 [patent_doc_number] => 11742041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks [patent_app_type] => utility [patent_app_number] => 17/655447 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 18437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655447
Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks Mar 17, 2022 Issued
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