Search

Mohammed A. Hasan

Examiner (ID: 12948, Phone: (571)272-2331 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
2776
Issued Applications
2500
Pending Applications
106
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11731693 [patent_doc_number] => 20170193136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'ON-CHIP AND SYSTEM-AREA MULTI-PROCESSOR INTERCONNECTION NETWORKS IN ADVANCED PROCESSES FOR MAXIMIZING PERFORMANCE MINIMIZING COST AND ENERGY' [patent_app_type] => utility [patent_app_number] => 15/445844 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13748 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445844 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445844
ON-CHIP AND SYSTEM-AREA MULTI-PROCESSOR INTERCONNECTION NETWORKS IN ADVANCED PROCESSES FOR MAXIMIZING PERFORMANCE MINIMIZING COST AND ENERGY Feb 27, 2017 Abandoned
Array ( [id] => 11945263 [patent_doc_number] => 20170249414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'Creating and Reusing Customizable Structured Interconnects' [patent_app_type] => utility [patent_app_number] => 15/445507 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445507
Creating and reusing customizable structured interconnects Feb 27, 2017 Issued
Array ( [id] => 14669913 [patent_doc_number] => 10372858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Design-for-testability (DFT) insertion at register-transfer-level (RTL) [patent_app_type] => utility [patent_app_number] => 15/445689 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5509 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445689 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445689
Design-for-testability (DFT) insertion at register-transfer-level (RTL) Feb 27, 2017 Issued
Array ( [id] => 14299331 [patent_doc_number] => 10289793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => System and method to generate schematics from layout-fabrics with a common cross-fabric model [patent_app_type] => utility [patent_app_number] => 15/445002 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 44 [patent_no_of_words] => 13195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445002
System and method to generate schematics from layout-fabrics with a common cross-fabric model Feb 27, 2017 Issued
Array ( [id] => 15733301 [patent_doc_number] => 10615084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Method and apparatus to determine a patterning process parameter, associated with a change in a physical configuration, using measured pixel optical characteristic values [patent_app_type] => utility [patent_app_number] => 15/445536 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 57 [patent_no_of_words] => 51704 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445536
Method and apparatus to determine a patterning process parameter, associated with a change in a physical configuration, using measured pixel optical characteristic values Feb 27, 2017 Issued
Array ( [id] => 13390931 [patent_doc_number] => 20180247008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => METHODOLOGY FOR MODEL-BASED SELF-ALIGNED VIA AWARENESS IN OPTICAL PROXIMITY CORRECTION [patent_app_type] => utility [patent_app_number] => 15/444899 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15444899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/444899
Methodology for model-based self-aligned via awareness in optical proximity correction Feb 27, 2017 Issued
Array ( [id] => 14394187 [patent_doc_number] => 10310372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-04 [patent_title] => Full-chip hierarchical inverse lithography [patent_app_type] => utility [patent_app_number] => 15/444118 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6474 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15444118 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/444118
Full-chip hierarchical inverse lithography Feb 26, 2017 Issued
Array ( [id] => 12053544 [patent_doc_number] => 20170329889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'METHOD FOR VERIFYING A LAYOUT DESIGNED FOR A SEMICONDUCTOR INTEGRATED CIRCUIT AND A COMPUTER SYSTEM FOR PERFORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/443195 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443195
Method for verifying a layout designed for a semiconductor integrated circuit and a computer system for performing the same Feb 26, 2017 Issued
Array ( [id] => 13285955 [patent_doc_number] => 10154581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Method for impedance compensation in printed circuit boards [patent_app_type] => utility [patent_app_number] => 15/428865 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2998 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428865 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428865
Method for impedance compensation in printed circuit boards Feb 8, 2017 Issued
Array ( [id] => 11652879 [patent_doc_number] => 20170148779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'Cell Circuit and Layout with Linear Finfet Structures' [patent_app_type] => utility [patent_app_number] => 15/426674 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426674 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426674
Cell circuit and layout with linear finfet structures Feb 6, 2017 Issued
Array ( [id] => 12516240 [patent_doc_number] => 10002881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Programmable integrated circuit standard cell [patent_app_type] => utility [patent_app_number] => 15/408753 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15207 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 441 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408753 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408753
Programmable integrated circuit standard cell Jan 17, 2017 Issued
Array ( [id] => 14642885 [patent_doc_number] => 10366187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Clock verification [patent_app_type] => utility [patent_app_number] => 15/404414 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404414 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/404414
Clock verification Jan 11, 2017 Issued
Array ( [id] => 13755083 [patent_doc_number] => 10170495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Stacked memory device, optical proximity correction (OPC) verifying method, method of designing layout of stacked memory device, and method of manufacturing stacked memory device [patent_app_type] => utility [patent_app_number] => 15/402258 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 13484 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15402258 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/402258
Stacked memory device, optical proximity correction (OPC) verifying method, method of designing layout of stacked memory device, and method of manufacturing stacked memory device Jan 9, 2017 Issued
Array ( [id] => 14601685 [patent_doc_number] => 10354035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Hot spot and process window monitoring [patent_app_type] => utility [patent_app_number] => 15/509728 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 6 [patent_no_of_words] => 4615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15509728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/509728
Hot spot and process window monitoring Jan 5, 2017 Issued
Array ( [id] => 14965681 [patent_doc_number] => 20190310319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => METHOD AND ARRANGMENT FOR CLASSIFYING A VOLTAGE FAULT CONDITION IN AN ELECTRICAL STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/461195 [patent_app_country] => US [patent_app_date] => 2016-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16461195 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/461195
Method and arrangment for classifying a voltage fault condition in an electrical storage system Nov 24, 2016 Issued
Array ( [id] => 11473218 [patent_doc_number] => 20170060001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'VERIFICATION METROLOGY TARGETS AND THEIR DESIGN' [patent_app_type] => utility [patent_app_number] => 15/351995 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5547 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/351995
Verification metrology target and their design Nov 14, 2016 Issued
Array ( [id] => 17700691 [patent_doc_number] => 11374427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Portable electronic device and wireless electric power transmission device [patent_app_type] => utility [patent_app_number] => 16/344685 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4471 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16344685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/344685
Portable electronic device and wireless electric power transmission device Oct 31, 2016 Issued
Array ( [id] => 15105409 [patent_doc_number] => 10474026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Method for correcting bevel corners of a layout pattern [patent_app_type] => utility [patent_app_number] => 15/335458 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3642 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335458 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335458
Method for correcting bevel corners of a layout pattern Oct 26, 2016 Issued
Array ( [id] => 12629409 [patent_doc_number] => 20180101633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => METHODS AND APPARATUS FOR DYNAMICALLY CONFIGURING SOFT PROCESSORS ON AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/287606 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287606
Methods and apparatus for dynamically configuring soft processors on an integrated circuit Oct 5, 2016 Issued
Array ( [id] => 14395807 [patent_doc_number] => 10311187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Circuit design method and simulation method based on random telegraph signal noise [patent_app_type] => utility [patent_app_number] => 15/287354 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287354 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287354
Circuit design method and simulation method based on random telegraph signal noise Oct 5, 2016 Issued
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