Mohammed A. Hasan

Array ( [id] => 12202984 [patent_doc_number] => 09906062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Cascading power for accessories' [patent_app_type] => utility [patent_app_number] => 14/962919 [patent_app_country] => US [patent_app_date] => 2015-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 20053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11279018 [patent_doc_number] => 09495497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-15 [patent_title] => 'Dynamic voltage frequency scaling' [patent_app_type] => utility [patent_app_number] => 14/960601 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14960601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14824323 [patent_doc_number] => 10409165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Optimization based on machine learning [patent_app_type] => utility [patent_app_number] => 15/528034 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10726180 [patent_doc_number] => 20160072328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'METHOD OF IMPROVING BATTERY RECHARGE EFFICIENCY BY STATISTICAL ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/942243 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7508 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10795756 [patent_doc_number] => 20160141913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'SYSTEM AND METHOD FOR RECONFIGURING A SOLAR PANEL FOR STORAGE AND TRANSPORT' [patent_app_type] => utility [patent_app_number] => 14/939949 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5370 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12101284 [patent_doc_number] => 09858381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Method of analog front end optimization in presence of circuit nonlinearity' [patent_app_type] => utility [patent_app_number] => 14/928952 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12571875 [patent_doc_number] => 10019546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-10 [patent_title] => Modular system on chip configuration system [patent_app_type] => utility [patent_app_number] => 14/928919 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11606939 [patent_doc_number] => 20170124242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'CONSTRUCTING FILL SHAPES FOR DOUBLE-PATTERNING TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 14/929113 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12979 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14929113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10778961 [patent_doc_number] => 20160125118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'COMPUTING RESOURCE ALLOCATION BASED ON FLOW GRAPH TRANSLATION' [patent_app_type] => utility [patent_app_number] => 14/928314 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8560 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10808761 [patent_doc_number] => 20160154920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'DESIGN METHOD AND DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/928808 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6626 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10778962 [patent_doc_number] => 20160125117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT THEREOF' [patent_app_type] => utility [patent_app_number] => 14/926128 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13653373 [patent_doc_number] => 09853007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Method for producing an integrated circuit package and apparatus produced thereby [patent_app_type] => utility [patent_app_number] => 14/926709 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6935 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703660 [patent_doc_number] => 20160049807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'Charger External Power Device Gain Sampling' [patent_app_type] => utility [patent_app_number] => 14/926777 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5855 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14176165 [patent_doc_number] => 10262098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Field programmable gate array bitstream verification [patent_app_type] => utility [patent_app_number] => 14/927046 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6467 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12174083 [patent_doc_number] => 09892227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Systems, methods and storage media for clock tree power estimation at register transfer level' [patent_app_type] => utility [patent_app_number] => 14/926619 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11686711 [patent_doc_number] => 09684759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'De-coupling capacitance placement' [patent_app_type] => utility [patent_app_number] => 14/925097 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4059 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11606936 [patent_doc_number] => 20170124240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'SCALABLE AND AUTOMATED IDENTIFICATION OF UNOBSERVABILITY CAUSALITY IN LOGIC OPTIMIZATION FLOWS' [patent_app_type] => utility [patent_app_number] => 14/924898 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10695953 [patent_doc_number] => 20160042099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'BEHAVIORAL SYNTHESIS APPARATUS, BEHAVIORAL SYNTHESIS METHOD, DATA PROCESSING SYSTEM INCLUDING BEHAVIORAL SYNTHESIS APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/922435 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14922435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10688476 [patent_doc_number] => 20160034620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/875593 [patent_app_country] => US [patent_app_date] => 2015-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7611 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10667524 [patent_doc_number] => 20160013669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'METHOD FOR EQUALIZING CAPACITIES OF ELECTRIC STORAGE DEVICES AND SYSTEM THEREOF' [patent_app_type] => utility [patent_app_number] => 14/858502 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8227 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858502 [rel_patent_id] =>[rel_patent_doc_number] =>)