Search

Mohammed A. Hasan

Examiner (ID: 12948, Phone: (571)272-2331 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2873, 2872
Total Applications
2776
Issued Applications
2500
Pending Applications
106
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10370996 [patent_doc_number] => 20150256002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SYSTEMS AND METHODS OF CONTROLLING BATTERY DETERIORATION BY CONTROLLING BATTERY TEMPERATURE DURING POWER EXCHANGE' [patent_app_type] => utility [patent_app_number] => 14/198708 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3934 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198708 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198708
Systems and methods of controlling battery deterioration by controlling battery temperature during power exchange Mar 5, 2014 Issued
Array ( [id] => 10370997 [patent_doc_number] => 20150256003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SYSTEMS AND METHODS OF CONTROLLING BATTERY DETERIORATION BY CONTROLLING BATTERY STATE-OF-HEALTH DURING POWER EXCHANGE' [patent_app_type] => utility [patent_app_number] => 14/198737 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4012 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198737 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198737
Systems and methods of controlling battery deterioration by controlling battery state-of-health during power exchange Mar 5, 2014 Issued
Array ( [id] => 11287047 [patent_doc_number] => 09502910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Power charging apparatus and battery apparatus' [patent_app_type] => utility [patent_app_number] => 14/199718 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4062 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199718 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/199718
Power charging apparatus and battery apparatus Mar 5, 2014 Issued
Array ( [id] => 9717345 [patent_doc_number] => 20140253043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'APPARATUS AND METHOD FOR WARNING CHARGE AMOUNT OF BATTERY' [patent_app_type] => utility [patent_app_number] => 14/197758 [patent_app_country] => US [patent_app_date] => 2014-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6719 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14197758 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/197758
APPARATUS AND METHOD FOR WARNING CHARGE AMOUNT OF BATTERY Mar 4, 2014 Abandoned
Array ( [id] => 10999432 [patent_doc_number] => 20160196379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'METROLOGY TARGET INDENTIFICATION, DESIGN AND VERIFICATION' [patent_app_type] => utility [patent_app_number] => 14/356551 [patent_app_country] => US [patent_app_date] => 2014-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11803 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356551 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356551
Metrology target identification, design and verification Mar 3, 2014 Issued
Array ( [id] => 10363514 [patent_doc_number] => 20150248519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'SYSTEM FOR PARTITIONING INTEGRATED CIRCUIT DESIGN BASED ON TIMING SLACK' [patent_app_type] => utility [patent_app_number] => 14/195827 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3940 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195827 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/195827
System for partitioning integrated circuit design based on timing slack Mar 2, 2014 Issued
Array ( [id] => 10682109 [patent_doc_number] => 20160028254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'SECONDARY BATTERY CHARGING SYSTEM AND METHOD, AND BATTERY PACK' [patent_app_type] => utility [patent_app_number] => 14/775699 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6514 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14775699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/775699
Secondary battery charging system and method, and battery pack Feb 26, 2014 Issued
Array ( [id] => 10342641 [patent_doc_number] => 20150227646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'PLACEMENT OF SINGLE-BIT AND MULTI-BIT FLIP-FLOPS' [patent_app_type] => utility [patent_app_number] => 14/192413 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 15469 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192413 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192413
Placement of single-bit and multi-bit flip-flops Feb 26, 2014 Issued
Array ( [id] => 10349958 [patent_doc_number] => 20150234963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'INTERFACE ANALYSIS FOR VERIFICATION OF DIGITAL CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/182626 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182626 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/182626
INTERFACE ANALYSIS FOR VERIFICATION OF DIGITAL CIRCUITS Feb 17, 2014 Abandoned
Array ( [id] => 10349968 [patent_doc_number] => 20150234973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'SYSTEM AND METHOD FOR ABSTRACTION OF A CIRCUIT PORTION OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/181476 [patent_app_country] => US [patent_app_date] => 2014-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2304 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14181476 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/181476
SYSTEM AND METHOD FOR ABSTRACTION OF A CIRCUIT PORTION OF AN INTEGRATED CIRCUIT Feb 13, 2014 Abandoned
Array ( [id] => 10550559 [patent_doc_number] => 09275185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Methods and systems for computer aided design of 3D integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/161895 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 11298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161895 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161895
Methods and systems for computer aided design of 3D integrated circuits Jan 22, 2014 Issued
Array ( [id] => 10682112 [patent_doc_number] => 20160028257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'BATTERY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/775303 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3699 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14775303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/775303
Battery system Jan 21, 2014 Issued
Array ( [id] => 9479595 [patent_doc_number] => 20140137058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'VALIDATION OF CIRCUIT DEFINITIONS' [patent_app_type] => utility [patent_app_number] => 14/160859 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9000 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160859 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160859
Validation of circuit definitions Jan 21, 2014 Issued
Array ( [id] => 10194998 [patent_doc_number] => 09223910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-29 [patent_title] => 'Performance and memory efficient modeling of HDL ports for simulation' [patent_app_type] => utility [patent_app_number] => 14/159855 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159855 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159855
Performance and memory efficient modeling of HDL ports for simulation Jan 20, 2014 Issued
Array ( [id] => 10550558 [patent_doc_number] => 09275184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-01 [patent_title] => 'Method and apparatus for performing timing closure analysis when performing register retiming' [patent_app_type] => utility [patent_app_number] => 14/159905 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159905 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159905
Method and apparatus for performing timing closure analysis when performing register retiming Jan 20, 2014 Issued
Array ( [id] => 9605012 [patent_doc_number] => 20140201694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'Wrap Based Fill In Layout Designs' [patent_app_type] => utility [patent_app_number] => 14/156445 [patent_app_country] => US [patent_app_date] => 2014-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6088 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14156445 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/156445
Wrap Based Fill In Layout Designs Jan 14, 2014 Abandoned
Array ( [id] => 9673577 [patent_doc_number] => 20140237441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'Method and Apparatus for Placing and Routing Partial Reconfiguration Modules' [patent_app_type] => utility [patent_app_number] => 14/152624 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152624 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152624
Method and apparatus for placing and routing partial reconfiguration modules Jan 9, 2014 Issued
Array ( [id] => 10292547 [patent_doc_number] => 20150177546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'COLOR CAST COMPENSATION METHOD AND SYSTEM FOR LIQUID CRYSTAL DISPLAY PANEL' [patent_app_type] => utility [patent_app_number] => 14/239337 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4618 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14239337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/239337
Color cast compensation method and system for liquid crystal display panel Jan 5, 2014 Issued
Array ( [id] => 10137803 [patent_doc_number] => 09171124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Parasitic extraction in an integrated circuit with multi-patterning requirements' [patent_app_type] => utility [patent_app_number] => 14/139023 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7063 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139023 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139023
Parasitic extraction in an integrated circuit with multi-patterning requirements Dec 22, 2013 Issued
Array ( [id] => 9752383 [patent_doc_number] => 08843873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-23 [patent_title] => 'Capacitive cell load estimation using electromigration analysis' [patent_app_type] => utility [patent_app_number] => 14/100005 [patent_app_country] => US [patent_app_date] => 2013-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2969 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100005 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100005
Capacitive cell load estimation using electromigration analysis Dec 7, 2013 Issued
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