Search

Mohammed A. Hasan

Examiner (ID: 15623, Phone: (571)272-2331 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2872, 2873
Total Applications
2820
Issued Applications
2524
Pending Applications
120
Abandoned Applications
206

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5275575 [patent_doc_number] => 20090127707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/269300 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6914 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127707.pdf [firstpage_image] =>[orig_patent_app_number] => 12269300 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/269300
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Nov 11, 2008 Abandoned
Array ( [id] => 8715115 [patent_doc_number] => 08401261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Imaging facial signs of neuro-physiological responses' [patent_app_type] => utility [patent_app_number] => 12/237889 [patent_app_country] => US [patent_app_date] => 2008-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6218 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12237889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237889
Imaging facial signs of neuro-physiological responses Sep 24, 2008 Issued
Array ( [id] => 5557377 [patent_doc_number] => 20090268954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'IMAGE PROCESSING APPARATUS AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/236934 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4295 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20090268954.pdf [firstpage_image] =>[orig_patent_app_number] => 12236934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236934
Image processing apparatus and program Sep 23, 2008 Issued
Array ( [id] => 6365036 [patent_doc_number] => 20100074480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'DEVICE FOR GENERATING ALTERNATIVE OF NORMAL BRAIN DATABASE' [patent_app_type] => utility [patent_app_number] => 12/234910 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 8590 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20100074480.pdf [firstpage_image] =>[orig_patent_app_number] => 12234910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/234910
DEVICE FOR GENERATING ALTERNATIVE OF NORMAL BRAIN DATABASE Sep 21, 2008 Abandoned
Array ( [id] => 5427741 [patent_doc_number] => 20090087051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Image Quality for Diagnostic Resolution Digital Slide Images' [patent_app_type] => utility [patent_app_number] => 12/234446 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7988 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20090087051.pdf [firstpage_image] =>[orig_patent_app_number] => 12234446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/234446
Image quality for diagnostic resolution digital slide images Sep 18, 2008 Issued
Array ( [id] => 5270500 [patent_doc_number] => 20090074276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Voxel Matching Technique for Removal of Artifacts in Medical Subtraction Images' [patent_app_type] => utility [patent_app_number] => 12/233031 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6143 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20090074276.pdf [firstpage_image] =>[orig_patent_app_number] => 12233031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233031
Voxel Matching Technique for Removal of Artifacts in Medical Subtraction Images Sep 17, 2008 Abandoned
Array ( [id] => 7801546 [patent_doc_number] => 08129820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/229809 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2583 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129820.pdf [firstpage_image] =>[orig_patent_app_number] => 12229809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/229809
Semiconductor device Aug 26, 2008 Issued
Array ( [id] => 4946926 [patent_doc_number] => 20080303052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'LIGHT EMITTING DIODE PACKAGE HAVING MULTIPLE MOLDING RESINS' [patent_app_type] => utility [patent_app_number] => 12/196028 [patent_app_country] => US [patent_app_date] => 2008-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8909 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303052.pdf [firstpage_image] =>[orig_patent_app_number] => 12196028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/196028
Light emitting diode package with a heat sink support ring and having multiple molding resins, wherein secondary molding resin with higher hardness than primary molding resin and which covers primary molding resin that covers LED die Aug 20, 2008 Issued
Array ( [id] => 5549812 [patent_doc_number] => 20090283798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/213469 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17435 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20090283798.pdf [firstpage_image] =>[orig_patent_app_number] => 12213469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213469
Semiconductor device and manufacturing method thereof Jun 18, 2008 Issued
Array ( [id] => 5360740 [patent_doc_number] => 20090035534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Method and structure of a reusable substrate' [patent_app_type] => utility [patent_app_number] => 12/155870 [patent_app_country] => US [patent_app_date] => 2008-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3175 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035534.pdf [firstpage_image] =>[orig_patent_app_number] => 12155870 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155870
Method and structure of a reusable substrate Jun 10, 2008 Abandoned
Array ( [id] => 4542734 [patent_doc_number] => 07875899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Light-emitting diode package and lead group structure for light-emitting diode package' [patent_app_type] => utility [patent_app_number] => 12/302669 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8163 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875899.pdf [firstpage_image] =>[orig_patent_app_number] => 12302669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/302669
Light-emitting diode package and lead group structure for light-emitting diode package Jan 6, 2008 Issued
Array ( [id] => 5358066 [patent_doc_number] => 20090032860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'PROGRAMMABLE MEMORY, PROGRAMMABLE MEMORY CELL AND THE MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/960720 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2968 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20090032860.pdf [firstpage_image] =>[orig_patent_app_number] => 11960720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960720
PROGRAMMABLE MEMORY, PROGRAMMABLE MEMORY CELL AND THE MANUFACTURING METHOD THEREOF Dec 19, 2007 Abandoned
Array ( [id] => 4503400 [patent_doc_number] => 07919795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating the thin film transistor substrate' [patent_app_type] => utility [patent_app_number] => 11/961149 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 8188 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/919/07919795.pdf [firstpage_image] =>[orig_patent_app_number] => 11961149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961149
Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating the thin film transistor substrate Dec 19, 2007 Issued
Array ( [id] => 4843246 [patent_doc_number] => 20080179654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 11/959919 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179654.pdf [firstpage_image] =>[orig_patent_app_number] => 11959919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959919
Nonvolatile semiconductor memory having transistor with a diffusion blocking layer between the lower gate and fully silicided upper gate Dec 18, 2007 Issued
Array ( [id] => 5542759 [patent_doc_number] => 20090152636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 11/954749 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3295 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20090152636.pdf [firstpage_image] =>[orig_patent_app_number] => 11954749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954749
HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS Dec 11, 2007 Abandoned
Array ( [id] => 9844884 [patent_doc_number] => 08946803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Method of forming a floating gate with a wide base and a narrow stem' [patent_app_type] => utility [patent_app_number] => 11/951998 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5033 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11951998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951998
Method of forming a floating gate with a wide base and a narrow stem Dec 5, 2007 Issued
Array ( [id] => 5419788 [patent_doc_number] => 20090146242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'METAL ION TRANSISTOR AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 11/951579 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3779 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20090146242.pdf [firstpage_image] =>[orig_patent_app_number] => 11951579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951579
Metal ion transistor Dec 5, 2007 Issued
Array ( [id] => 4558001 [patent_doc_number] => 07838395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same' [patent_app_type] => utility [patent_app_number] => 11/951729 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4364 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838395.pdf [firstpage_image] =>[orig_patent_app_number] => 11951729 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951729
Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same Dec 5, 2007 Issued
Array ( [id] => 9844958 [patent_doc_number] => 08946878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Integrated circuit package-in-package system housing a plurality of stacked and offset integrated circuits and method of manufacture therefor' [patent_app_type] => utility [patent_app_number] => 11/951958 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3702 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 470 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11951958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951958
Integrated circuit package-in-package system housing a plurality of stacked and offset integrated circuits and method of manufacture therefor Dec 5, 2007 Issued
Array ( [id] => 4462383 [patent_doc_number] => 07880266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Four-terminal antifuse structure having integrated heating elements for a programmable circuit' [patent_app_type] => utility [patent_app_number] => 11/949569 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8168 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/880/07880266.pdf [firstpage_image] =>[orig_patent_app_number] => 11949569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949569
Four-terminal antifuse structure having integrated heating elements for a programmable circuit Dec 2, 2007 Issued
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