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Mohammed Alam

Examiner (ID: 8758)

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1049
Issued Applications
924
Pending Applications
68
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18119583 [patent_doc_number] => 11550978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Circuit design assistance system and computer readable medium [patent_app_type] => utility [patent_app_number] => 17/223466 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7872 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223466 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223466
Circuit design assistance system and computer readable medium Apr 5, 2021 Issued
Array ( [id] => 18291547 [patent_doc_number] => 11620417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-04 [patent_title] => User interface for interactive skew group analysis [patent_app_type] => utility [patent_app_number] => 17/219765 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219765
User interface for interactive skew group analysis Mar 30, 2021 Issued
Array ( [id] => 17637199 [patent_doc_number] => 11347923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => Buffering algorithm with maximum cost constraint [patent_app_type] => utility [patent_app_number] => 17/219737 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219737
Buffering algorithm with maximum cost constraint Mar 30, 2021 Issued
Array ( [id] => 18053258 [patent_doc_number] => 11526643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-13 [patent_title] => Enumerating coverage based on an architectural specification [patent_app_type] => utility [patent_app_number] => 17/301184 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9582 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301184
Enumerating coverage based on an architectural specification Mar 28, 2021 Issued
Array ( [id] => 16964518 [patent_doc_number] => 20210216017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SELECTION OF MEASUREMENT LOCATIONS FOR PATTERNING PROCESSES [patent_app_type] => utility [patent_app_number] => 17/214456 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214456 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214456
Selection of measurement locations for patterning processes Mar 25, 2021 Issued
Array ( [id] => 18031029 [patent_doc_number] => 11514219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-29 [patent_title] => System and method for assertion-based formal verification using cached metadata [patent_app_type] => utility [patent_app_number] => 17/212150 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212150
System and method for assertion-based formal verification using cached metadata Mar 24, 2021 Issued
Array ( [id] => 18053257 [patent_doc_number] => 11526642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-13 [patent_title] => Clock network power estimation for logical designs [patent_app_type] => utility [patent_app_number] => 17/210271 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6435 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210271
Clock network power estimation for logical designs Mar 22, 2021 Issued
Array ( [id] => 18951405 [patent_doc_number] => 11894713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Power supply circuit providing control over adaptive charging and charging capability, power supply unit thereof, and charging control method thereof [patent_app_type] => utility [patent_app_number] => 17/200884 [patent_app_country] => US [patent_app_date] => 2021-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6547 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200884
Power supply circuit providing control over adaptive charging and charging capability, power supply unit thereof, and charging control method thereof Mar 13, 2021 Issued
Array ( [id] => 17622249 [patent_doc_number] => 11341306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Method for building spice circuit model of an optical coupler [patent_app_type] => utility [patent_app_number] => 17/199450 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6210 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199450
Method for building spice circuit model of an optical coupler Mar 11, 2021 Issued
Array ( [id] => 19812738 [patent_doc_number] => 12244151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Wireless power transfer in modular systems [patent_app_type] => utility [patent_app_number] => 17/198978 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7402 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198978
Wireless power transfer in modular systems Mar 10, 2021 Issued
Array ( [id] => 17346070 [patent_doc_number] => 20220012401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME [patent_app_type] => utility [patent_app_number] => 17/199023 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199023
Method of manufacturing semiconductor device and system for same Mar 10, 2021 Issued
Array ( [id] => 17231004 [patent_doc_number] => 20210357561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT [patent_app_type] => utility [patent_app_number] => 17/195953 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195953
Systems and methods for integrated circuit layout Mar 8, 2021 Issued
Array ( [id] => 18782594 [patent_doc_number] => 11824365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Portable blender with wireless charging [patent_app_type] => utility [patent_app_number] => 17/195338 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 544 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195338
Portable blender with wireless charging Mar 7, 2021 Issued
Array ( [id] => 17476215 [patent_doc_number] => 20220083719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => LOGIC SIMULATION VERIFICATION SYSTEM, LOGIC SIMULATION VERIFICATION METHOD, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 17/190097 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190097
Logic simulation verification system, logic simulation verification method, and program Mar 1, 2021 Issued
Array ( [id] => 17839817 [patent_doc_number] => 20220277122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Soft Error-Mitigating Semiconductor Design System and Associated Methods [patent_app_type] => utility [patent_app_number] => 17/187516 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187516
Soft error-mitigating semiconductor design system and associated methods Feb 25, 2021 Issued
Array ( [id] => 18668808 [patent_doc_number] => 11775712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-03 [patent_title] => Determining mechanical reliability of electronic packages assembled with thermal pads [patent_app_type] => utility [patent_app_number] => 17/179767 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179767
Determining mechanical reliability of electronic packages assembled with thermal pads Feb 18, 2021 Issued
Array ( [id] => 18087638 [patent_doc_number] => 11537775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Timing and placement co-optimization for engineering change order (ECO) cells [patent_app_type] => utility [patent_app_number] => 17/176987 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 6469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176987
Timing and placement co-optimization for engineering change order (ECO) cells Feb 15, 2021 Issued
Array ( [id] => 17346072 [patent_doc_number] => 20220012403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR CHIP DESIGN METHOD AND COMPUTING DEVICE FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/171267 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171267 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171267
Semiconductor chip design method and computing device for performing the same Feb 8, 2021 Issued
Array ( [id] => 17606211 [patent_doc_number] => 11334701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Method for comprehensive integration verification of mixed-signal circuits [patent_app_type] => utility [patent_app_number] => 17/168230 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5143 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168230
Method for comprehensive integration verification of mixed-signal circuits Feb 4, 2021 Issued
Array ( [id] => 17907668 [patent_doc_number] => 11461523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-04 [patent_title] => Glitch analysis and glitch power estimation system [patent_app_type] => utility [patent_app_number] => 17/169375 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13045 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169375
Glitch analysis and glitch power estimation system Feb 4, 2021 Issued
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