
Mohammed Alam
Examiner (ID: 8758)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 1049 |
| Issued Applications | 924 |
| Pending Applications | 68 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18086914
[patent_doc_number] => 11537043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-27
[patent_title] => Reduction or elimination of pattern placement error in metrology measurements
[patent_app_type] => utility
[patent_app_number] => 17/161645
[patent_app_country] => US
[patent_app_date] => 2021-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6232
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161645
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/161645 | Reduction or elimination of pattern placement error in metrology measurements | Jan 27, 2021 | Issued |
Array
(
[id] => 16994322
[patent_doc_number] => 20210232742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-29
[patent_title] => DETECTING TIMING VIOLATIONS IN EMULATION USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) REPROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 17/159056
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10640
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159056
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/159056 | Detecting timing violations in emulation using field programmable gate array (FPGA) reprogramming | Jan 25, 2021 | Issued |
Array
(
[id] => 17528921
[patent_doc_number] => 11301610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Methods for modeling of a design in reticle enhancement technology
[patent_app_type] => utility
[patent_app_number] => 17/248325
[patent_app_country] => US
[patent_app_date] => 2021-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 25
[patent_no_of_words] => 21530
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248325
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/248325 | Methods for modeling of a design in reticle enhancement technology | Jan 19, 2021 | Issued |
Array
(
[id] => 20081011
[patent_doc_number] => 12355089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Battery module and battery pack including the same
[patent_app_type] => utility
[patent_app_number] => 17/641325
[patent_app_country] => US
[patent_app_date] => 2021-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 0
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17641325
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/641325 | Battery module and battery pack including the same | Jan 14, 2021 | Issued |
Array
(
[id] => 17682694
[patent_doc_number] => 11366950
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-06-21
[patent_title] => Tiled datamesh architecture
[patent_app_type] => utility
[patent_app_number] => 17/148941
[patent_app_country] => US
[patent_app_date] => 2021-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6736
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148941
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/148941 | Tiled datamesh architecture | Jan 13, 2021 | Issued |
Array
(
[id] => 19428749
[patent_doc_number] => 12088188
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Wireless charging control method, and wireless charging transmitter and system
[patent_app_type] => utility
[patent_app_number] => 17/144764
[patent_app_country] => US
[patent_app_date] => 2021-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11433
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144764
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/144764 | Wireless charging control method, and wireless charging transmitter and system | Jan 7, 2021 | Issued |
Array
(
[id] => 17238644
[patent_doc_number] => 11182524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-11-23
[patent_title] => Fixing device for clock tree and fixing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/144165
[patent_app_country] => US
[patent_app_date] => 2021-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 3983
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144165
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/144165 | Fixing device for clock tree and fixing method thereof | Jan 7, 2021 | Issued |
Array
(
[id] => 17651753
[patent_doc_number] => 11354483
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-06-07
[patent_title] => Parasitic representation of large scale IC packages and boards
[patent_app_type] => utility
[patent_app_number] => 17/142381
[patent_app_country] => US
[patent_app_date] => 2021-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6835
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142381
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/142381 | Parasitic representation of large scale IC packages and boards | Jan 5, 2021 | Issued |
Array
(
[id] => 17528923
[patent_doc_number] => 11301612
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-04-12
[patent_title] => Method and apparatus for predicting electrical values in electronic circuits
[patent_app_type] => utility
[patent_app_number] => 17/140086
[patent_app_country] => US
[patent_app_date] => 2021-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 7332
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140086
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/140086 | Method and apparatus for predicting electrical values in electronic circuits | Jan 2, 2021 | Issued |
Array
(
[id] => 17573241
[patent_doc_number] => 11321514
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-05-03
[patent_title] => Macro clock latency computation in multiple iteration clock tree synthesis
[patent_app_type] => utility
[patent_app_number] => 17/139612
[patent_app_country] => US
[patent_app_date] => 2020-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6369
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139612
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/139612 | Macro clock latency computation in multiple iteration clock tree synthesis | Dec 30, 2020 | Issued |
Array
(
[id] => 17395085
[patent_doc_number] => 11244099
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-02-08
[patent_title] => Machine-learning based prediction method for iterative clustering during clock tree synthesis
[patent_app_type] => utility
[patent_app_number] => 17/139675
[patent_app_country] => US
[patent_app_date] => 2020-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7105
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139675
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/139675 | Machine-learning based prediction method for iterative clustering during clock tree synthesis | Dec 30, 2020 | Issued |
Array
(
[id] => 17253209
[patent_doc_number] => 11188702
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-11-30
[patent_title] => Dynamic weighting scheme for local cluster refinement
[patent_app_type] => utility
[patent_app_number] => 17/139617
[patent_app_country] => US
[patent_app_date] => 2020-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7208
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139617
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/139617 | Dynamic weighting scheme for local cluster refinement | Dec 30, 2020 | Issued |
Array
(
[id] => 18473903
[patent_doc_number] => 20230208191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => MOBILE COMPUTING DEVICE ENCLOSURE WITH EMBEDDED WIRELESS CHARGING MODULE
[patent_app_type] => utility
[patent_app_number] => 17/998471
[patent_app_country] => US
[patent_app_date] => 2020-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11364
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998471
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/998471 | MOBILE COMPUTING DEVICE ENCLOSURE WITH EMBEDDED WIRELESS CHARGING MODULE | Dec 29, 2020 | Pending |
Array
(
[id] => 19855100
[patent_doc_number] => 12257915
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Charging of an AGV
[patent_app_type] => utility
[patent_app_number] => 18/259027
[patent_app_country] => US
[patent_app_date] => 2020-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2022
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18259027
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/259027 | Charging of an AGV | Dec 28, 2020 | Issued |
Array
(
[id] => 16765976
[patent_doc_number] => 20210111558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => ENERGY STORAGE SYSTEM AND SELF-START METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/129609
[patent_app_country] => US
[patent_app_date] => 2020-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5942
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129609
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/129609 | Energy storage system and self-start method thereof | Dec 20, 2020 | Issued |
Array
(
[id] => 17675332
[patent_doc_number] => 20220188499
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => INTEGRATED INPUT/OUTPUT PAD AND ANALOG MULTIPLEXER ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 17/124283
[patent_app_country] => US
[patent_app_date] => 2020-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3251
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124283
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/124283 | Integrated input/output pad and analog multiplexer architecture | Dec 15, 2020 | Issued |
Array
(
[id] => 17499719
[patent_doc_number] => 11288425
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-03-29
[patent_title] => Path-based timing driven placement using iterative pseudo netlist changes
[patent_app_type] => utility
[patent_app_number] => 17/124429
[patent_app_country] => US
[patent_app_date] => 2020-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10876
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124429
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/124429 | Path-based timing driven placement using iterative pseudo netlist changes | Dec 15, 2020 | Issued |
Array
(
[id] => 16730080
[patent_doc_number] => 20210097227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-01
[patent_title] => ELECTROMIGRATION EVALUATION METHODOLOGY WITH CONSIDERATION OF BOTH SELF-HEATING AND HEAT SINK THERMAL EFFECTS
[patent_app_type] => utility
[patent_app_number] => 17/121312
[patent_app_country] => US
[patent_app_date] => 2020-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9821
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121312
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/121312 | Electromigration evaluation methodology with consideration of both self-heating and heat sink thermal effects | Dec 13, 2020 | Issued |
Array
(
[id] => 17515900
[patent_doc_number] => 11295055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-05
[patent_title] => Transmission gate structure and method
[patent_app_type] => utility
[patent_app_number] => 17/116745
[patent_app_country] => US
[patent_app_date] => 2020-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 24274
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116745
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/116745 | Transmission gate structure and method | Dec 8, 2020 | Issued |
Array
(
[id] => 16722549
[patent_doc_number] => 20210089696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => SYSTEM AND METHOD FOR ESL MODELING OF MACHINE LEARNING
[patent_app_type] => utility
[patent_app_number] => 17/115407
[patent_app_country] => US
[patent_app_date] => 2020-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8700
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115407
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/115407 | System and method for ESL modeling of machine learning | Dec 7, 2020 | Issued |