Search

Mohammed Alam

Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1059
Issued Applications
934
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14036761 [patent_doc_number] => 10230142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Energy generation system combining a fuel cell and a rechargeable battery and methods implementing such a system [patent_app_type] => utility [patent_app_number] => 15/327589 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4388 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15327589 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/327589
Energy generation system combining a fuel cell and a rechargeable battery and methods implementing such a system Jul 22, 2015 Issued
Array ( [id] => 11674205 [patent_doc_number] => 20170162929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'Charging Cable' [patent_app_type] => utility [patent_app_number] => 15/327528 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4469 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15327528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/327528
Charging Cable Jul 20, 2015 Abandoned
Array ( [id] => 11669359 [patent_doc_number] => 20170158079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'ELECTRIC VEHICLE QUICK CHARGE CONTROL APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/327431 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3990 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15327431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/327431
Electric vehicle quick charge control apparatus Jul 12, 2015 Issued
Array ( [id] => 11897310 [patent_doc_number] => 09767247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Look-up table restructuring for timing closure in circuit designs' [patent_app_type] => utility [patent_app_number] => 14/798269 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 12344 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798269 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/798269
Look-up table restructuring for timing closure in circuit designs Jul 12, 2015 Issued
Array ( [id] => 11397210 [patent_doc_number] => 20170017746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG NETWORK CREATION FOR HIERARCHICAL CIRCUIT DESIGNS' [patent_app_type] => utility [patent_app_number] => 14/798250 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5614 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/798250
Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs Jul 12, 2015 Issued
Array ( [id] => 11810996 [patent_doc_number] => 09715567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Systems and methods for full-order equivalent circuit approach (ECA) modeling of layered structures' [patent_app_type] => utility [patent_app_number] => 14/796427 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5533 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14796427 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/796427
Systems and methods for full-order equivalent circuit approach (ECA) modeling of layered structures Jul 9, 2015 Issued
Array ( [id] => 11811000 [patent_doc_number] => 09715570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Systems and methods for modeling asymmetric vias' [patent_app_type] => utility [patent_app_number] => 14/796232 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6766 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14796232 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/796232
Systems and methods for modeling asymmetric vias Jul 9, 2015 Issued
Array ( [id] => 11659307 [patent_doc_number] => 09672310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-06 [patent_title] => 'Reliability guardband compensation' [patent_app_type] => utility [patent_app_number] => 14/795013 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14795013 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/795013
Reliability guardband compensation Jul 8, 2015 Issued
Array ( [id] => 11385106 [patent_doc_number] => 20170011162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'HIERARCHICAL WIRE-PIN CO-OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/794871 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4739 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794871 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794871
Hierarchical wire-pin co-optimization Jul 8, 2015 Issued
Array ( [id] => 11385100 [patent_doc_number] => 20170011156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'CONTROL PATH POWER ADJUSTMENT FOR CHIP DESIGN' [patent_app_type] => utility [patent_app_number] => 14/795254 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5047 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14795254 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/795254
Control path power adjustment for chip design Jul 8, 2015 Issued
Array ( [id] => 13292121 [patent_doc_number] => 10157256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Systems and methods for identifying wires for adjustment [patent_app_type] => utility [patent_app_number] => 14/793918 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793918 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793918
Systems and methods for identifying wires for adjustment Jul 7, 2015 Issued
Array ( [id] => 11817106 [patent_doc_number] => 09721058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'System and method for reactive initialization based formal verification of electronic logic design' [patent_app_type] => utility [patent_app_number] => 14/794549 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3883 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794549 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794549
System and method for reactive initialization based formal verification of electronic logic design Jul 7, 2015 Issued
Array ( [id] => 11739338 [patent_doc_number] => 09703921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-11 [patent_title] => 'Naturally connecting mixed-signal power networks in mixed-signal simulations' [patent_app_type] => utility [patent_app_number] => 14/794558 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794558 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794558
Naturally connecting mixed-signal power networks in mixed-signal simulations Jul 7, 2015 Issued
Array ( [id] => 10393413 [patent_doc_number] => 20150278420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Stretch Dummy Cell Insertion in FinFET Process' [patent_app_type] => utility [patent_app_number] => 14/739108 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14739108 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/739108
Stretch dummy cell insertion in finFET process Jun 14, 2015 Issued
Array ( [id] => 11584995 [patent_doc_number] => 09639640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-02 [patent_title] => 'Generation of delay values for a simulation model of circuit elements in a clock network' [patent_app_type] => utility [patent_app_number] => 14/693506 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14693506 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/693506
Generation of delay values for a simulation model of circuit elements in a clock network Apr 21, 2015 Issued
Array ( [id] => 10477817 [patent_doc_number] => 20150362834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'EXPOSURE METHODS USING E-BEAMS AND METHODS OF MANUFACTURING MASKS AND SEMICONDUCTOR DEVICES THEREFROM' [patent_app_type] => utility [patent_app_number] => 14/693429 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11318 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14693429 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/693429
Exposure methods using e-beams and methods of manufacturing masks and semiconductor devices therefrom Apr 21, 2015 Issued
Array ( [id] => 10709142 [patent_doc_number] => 20160055289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'Verification Of Photonic Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 14/693851 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5579 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14693851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/693851
Verification of photonic integrated circuits Apr 21, 2015 Issued
Array ( [id] => 11117262 [patent_doc_number] => 20160314236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'Method of Hierarchical Timing Closure Employing Dynamic Load-Sensitive Feedback Constraints' [patent_app_type] => utility [patent_app_number] => 14/691599 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4362 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691599 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/691599
Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints Apr 20, 2015 Issued
Array ( [id] => 11791231 [patent_doc_number] => 09400863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'Color-insensitive rules for routing structures' [patent_app_type] => utility [patent_app_number] => 14/687477 [patent_app_country] => US [patent_app_date] => 2015-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4460 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14687477 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/687477
Color-insensitive rules for routing structures Apr 14, 2015 Issued
Array ( [id] => 12951310 [patent_doc_number] => 09836564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Efficient extraction of the worst sample in Monte Carlo simulation [patent_app_type] => utility [patent_app_number] => 14/683021 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683021 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/683021
Efficient extraction of the worst sample in Monte Carlo simulation Apr 8, 2015 Issued
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