Mohammed Alam

Array ( [id] => 11577887 [patent_doc_number] => 09633150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Experiments approach to design variation mitigation and optimization' [patent_app_type] => utility [patent_app_number] => 14/681554 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10264 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10401763 [patent_doc_number] => 20150286772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'Method and system for computer-aided design of radiation-hardened integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/681028 [patent_app_country] => US [patent_app_date] => 2015-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11345551 [patent_doc_number] => 09529960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Photolithography patterning system using feature parameters' [patent_app_type] => utility [patent_app_number] => 14/679710 [patent_app_country] => US [patent_app_date] => 2015-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 8692 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14679710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10401762 [patent_doc_number] => 20150286771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'CATEGORIZED STITCHING GUIDANCE FOR TRIPLE-PATTERNING TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 14/678831 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13422 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10717025 [patent_doc_number] => 20160063172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'Connectivity-Aware Layout Data Reduction For Design Verification' [patent_app_type] => utility [patent_app_number] => 14/663275 [patent_app_country] => US [patent_app_date] => 2015-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6962 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14663275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11299895 [patent_doc_number] => 09507903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method for estimation of delays and slews during circuit optimization' [patent_app_type] => utility [patent_app_number] => 14/662577 [patent_app_country] => US [patent_app_date] => 2015-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14662577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11345542 [patent_doc_number] => 09529950 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'Systems and methods for performing profile-based circuit optimization using high-level system modeling' [patent_app_type] => utility [patent_app_number] => 14/661750 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9551 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14661750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11079882 [patent_doc_number] => 20160276846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'STORAGE BATTERY MANAGEMENT DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/771962 [patent_app_country] => US [patent_app_date] => 2015-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3228 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14771962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11847508 [patent_doc_number] => 09735065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Systems and methods of local focus error compensation for semiconductor processes' [patent_app_type] => utility [patent_app_number] => 14/656754 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 9645 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11048916 [patent_doc_number] => 20160245874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'BATTERY MANAGEMENT SYSTEM FOR OUTPUTTING SIGNAL, CAPABLE OF ANALYZING WHETHER ERROR HAS OCCURED, AND BATTERY DRIVING SYSTEM INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 15/024295 [patent_app_country] => US [patent_app_date] => 2015-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7595 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15024295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10236326 [patent_doc_number] => 20150121320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'System And Method For Universal Control Of Electronic Devices' [patent_app_type] => utility [patent_app_number] => 14/584897 [patent_app_country] => US [patent_app_date] => 2014-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10369 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10991709 [patent_doc_number] => 20160188654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'RULE BASED DATA NORMALIZATION UTILIZING MULTI-KEY SORTING' [patent_app_type] => utility [patent_app_number] => 14/582510 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11306637 [patent_doc_number] => 09514035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-06 [patent_title] => 'Coverage driven generation of constrained random stimuli' [patent_app_type] => utility [patent_app_number] => 14/582328 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3641 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11333119 [patent_doc_number] => 09524365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-20 [patent_title] => 'Efficient monte carlo flow via failure probability modeling' [patent_app_type] => utility [patent_app_number] => 14/581958 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11796046 [patent_doc_number] => 09405877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-02 [patent_title] => 'System and method of fast phase aligned local generation of clocks on multiple FPGA system' [patent_app_type] => utility [patent_app_number] => 14/580014 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5554 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10204474 [patent_doc_number] => 20150089462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'CONCURRENT OPTIMIZATION OF TIMING, AREA, AND LEAKAGE POWER' [patent_app_type] => utility [patent_app_number] => 14/557920 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10462627 [patent_doc_number] => 20150347643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/547324 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3944 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12173380 [patent_doc_number] => 09891519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Free form fracturing method for electronic or optical lithography using resist threshold control' [patent_app_type] => utility [patent_app_number] => 15/033016 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 6470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9841114 [patent_doc_number] => 20150033196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'Clustering For Processing Of Circuit Design Data' [patent_app_type] => utility [patent_app_number] => 14/504612 [patent_app_country] => US [patent_app_date] => 2014-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14504612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14460623 [patent_doc_number] => 10326288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Method and device for the voltage-controlled self-deactivation of electronic components or battery cells [patent_app_type] => utility [patent_app_number] => 15/028901 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4982 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15028901 [rel_patent_id] =>[rel_patent_doc_number] =>)