Search

Mohammed Alam

Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1059
Issued Applications
934
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11360670 [patent_doc_number] => 09537332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Apparatus, system and method for charge balancing of individual batteries in a string of batteries using battery voltage and temperature, and detecting and preventing thermal runaway' [patent_app_type] => utility [patent_app_number] => 14/292538 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5491 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292538 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/292538
Apparatus, system and method for charge balancing of individual batteries in a string of batteries using battery voltage and temperature, and detecting and preventing thermal runaway May 29, 2014 Issued
Array ( [id] => 10464558 [patent_doc_number] => 20150349573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'Single Stage Rectification and Regulation for Wireless Charging Systems' [patent_app_type] => utility [patent_app_number] => 14/292148 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292148 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/292148
Single stage rectification and regulation for wireless charging systems May 29, 2014 Issued
Array ( [id] => 13018883 [patent_doc_number] => 10032557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-24 [patent_title] => Tuning of primary and secondary resonant frequency for improved efficiency of inductive power transfer [patent_app_type] => utility [patent_app_number] => 14/290411 [patent_app_country] => US [patent_app_date] => 2014-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5159 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14290411 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/290411
Tuning of primary and secondary resonant frequency for improved efficiency of inductive power transfer May 28, 2014 Issued
Array ( [id] => 10462624 [patent_doc_number] => 20150347640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/288794 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4063 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288794 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/288794
Physical aware technology mapping in synthesis May 27, 2014 Issued
Array ( [id] => 11226909 [patent_doc_number] => 09454631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Stitch-derived via structures and methods of generating the same' [patent_app_type] => utility [patent_app_number] => 14/285719 [patent_app_country] => US [patent_app_date] => 2014-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14285719 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/285719
Stitch-derived via structures and methods of generating the same May 22, 2014 Issued
Array ( [id] => 10293418 [patent_doc_number] => 20150178417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'METHOD FOR SHOWING HIERARCHICAL STRUCTURE FOR A GIVEN POWER INTENT DESCRIBED IN A POWER INTENT DESCRIPTION LANGUAGE WITH A DESIGN DESCRIBED IN A HARDWARE DESIGN DESCRIPTION LANGUAGE, AND ASSOCIATED APPARATUS AND ASSOCIATED COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/284411 [patent_app_country] => US [patent_app_date] => 2014-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14284411 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/284411
Method for showing hierarchical structure for a given power intent described in a power intent description language with a design described in a hardware design description language, and associated apparatus and associated computer program product May 21, 2014 Issued
Array ( [id] => 9723258 [patent_doc_number] => 20140258959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'SUPPORT TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 14/284463 [patent_app_country] => US [patent_app_date] => 2014-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 11694 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14284463 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/284463
SUPPORT TECHNIQUE May 21, 2014 Abandoned
Array ( [id] => 10393411 [patent_doc_number] => 20150278418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'LOGIC ANALYZER CIRCUIT FOR PROGRAMMABLE LOGIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/283454 [patent_app_country] => US [patent_app_date] => 2014-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5088 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14283454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/283454
Logic analyzer circuit for programmable logic device May 20, 2014 Issued
Array ( [id] => 13651875 [patent_doc_number] => 09852253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Automated layout for integrated circuits with nonstandard cells [patent_app_type] => utility [patent_app_number] => 14/891659 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 10774 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14891659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/891659
Automated layout for integrated circuits with nonstandard cells May 18, 2014 Issued
Array ( [id] => 10860890 [patent_doc_number] => 08887108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-11 [patent_title] => 'Support apparatus, design support method, and recording medium' [patent_app_type] => utility [patent_app_number] => 14/277083 [patent_app_country] => US [patent_app_date] => 2014-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 26988 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14277083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/277083
Support apparatus, design support method, and recording medium May 13, 2014 Issued
Array ( [id] => 10111600 [patent_doc_number] => 09147017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Verification support method, recording medium having stored verification support program therein, and verification support apparatus' [patent_app_type] => utility [patent_app_number] => 14/276493 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7359 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14276493 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/276493
Verification support method, recording medium having stored verification support program therein, and verification support apparatus May 12, 2014 Issued
Array ( [id] => 10932610 [patent_doc_number] => 20140335631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'SEMICONDUCTOR DEFECT CHARACTERIZATION' [patent_app_type] => utility [patent_app_number] => 14/271331 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271331
Semiconductor defect characterization May 5, 2014 Issued
Array ( [id] => 10524791 [patent_doc_number] => 09251307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Circuit information processing device, circuit information processing system, database, non-transitory computer readable medium, and circuit design method' [patent_app_type] => utility [patent_app_number] => 14/267171 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6808 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267171 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267171
Circuit information processing device, circuit information processing system, database, non-transitory computer readable medium, and circuit design method Apr 30, 2014 Issued
Array ( [id] => 10623698 [patent_doc_number] => 09342641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Configuration of logic analyzer using graphical user interface' [patent_app_type] => utility [patent_app_number] => 14/266527 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3423 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266527 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/266527
Configuration of logic analyzer using graphical user interface Apr 29, 2014 Issued
Array ( [id] => 10425146 [patent_doc_number] => 20150310157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION' [patent_app_type] => utility [patent_app_number] => 14/263340 [patent_app_country] => US [patent_app_date] => 2014-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14263340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/263340
Mask error compensation by optical modeling calibration Apr 27, 2014 Issued
Array ( [id] => 10625448 [patent_doc_number] => 09344408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Cloud-basd digital verification system and method' [patent_app_type] => utility [patent_app_number] => 14/261671 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5107 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/261671
Cloud-basd digital verification system and method Apr 24, 2014 Issued
Array ( [id] => 10417119 [patent_doc_number] => 20150302129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'MASK ASSIGNMENT TECHNIQUE FOR M1 METAL LAYER IN TRIPLE-PATTERNING LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 14/255677 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3206 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255677 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255677
MASK ASSIGNMENT TECHNIQUE FOR M1 METAL LAYER IN TRIPLE-PATTERNING LITHOGRAPHY Apr 16, 2014 Abandoned
Array ( [id] => 10934789 [patent_doc_number] => 20140337811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'SUB-MODULE PHYSICAL REFINEMENT FLOW' [patent_app_type] => utility [patent_app_number] => 14/254143 [patent_app_country] => US [patent_app_date] => 2014-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7892 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14254143 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/254143
Sub-module physical refinement flow Apr 15, 2014 Issued
Array ( [id] => 11232297 [patent_doc_number] => 09459523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Pattern optical similarity determination' [patent_app_type] => utility [patent_app_number] => 14/253171 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8414 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253171 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253171
Pattern optical similarity determination Apr 14, 2014 Issued
Array ( [id] => 10409046 [patent_doc_number] => 20150294055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/253784 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3463 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253784 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253784
Systems and methods for increasing debugging visibility of prototyping systems Apr 14, 2014 Issued
Menu