
Mohammed Alam
Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 1059 |
| Issued Applications | 934 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10085488
[patent_doc_number] => 09122836
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-01
[patent_title] => 'Recognition of template patterns with mask information'
[patent_app_type] => utility
[patent_app_number] => 14/251696
[patent_app_country] => US
[patent_app_date] => 2014-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5958
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251696
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/251696 | Recognition of template patterns with mask information | Apr 13, 2014 | Issued |
Array
(
[id] => 10907648
[patent_doc_number] => 20140310662
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-16
[patent_title] => 'PATTERN INSPECTION METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/249843
[patent_app_country] => US
[patent_app_date] => 2014-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8456
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14249843
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/249843 | Pattern inspection method of semiconductor device optical image | Apr 9, 2014 | Issued |
Array
(
[id] => 10913725
[patent_doc_number] => 20140316744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-23
[patent_title] => 'ASSIGNING METHOD, RECORDING MEDIUM, INFORMATION PROCESSING APPARATUS, AND ANALYSIS SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/246203
[patent_app_country] => US
[patent_app_date] => 2014-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 38972
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14246203
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/246203 | Assigning method, recording medium, information processing apparatus, and analysis system | Apr 6, 2014 | Issued |
Array
(
[id] => 11616238
[patent_doc_number] => 09654109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-16
[patent_title] => 'Hardened programmable devices'
[patent_app_type] => utility
[patent_app_number] => 14/247030
[patent_app_country] => US
[patent_app_date] => 2014-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12007
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247030
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/247030 | Hardened programmable devices | Apr 6, 2014 | Issued |
Array
(
[id] => 10009766
[patent_doc_number] => 09053288
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-06-09
[patent_title] => 'Layout checking system for multiple-patterning group assignment constraints'
[patent_app_type] => utility
[patent_app_number] => 14/231273
[patent_app_country] => US
[patent_app_date] => 2014-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 4609
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231273
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/231273 | Layout checking system for multiple-patterning group assignment constraints | Mar 30, 2014 | Issued |
Array
(
[id] => 11775387
[patent_doc_number] => 09384317
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-07-05
[patent_title] => 'Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques'
[patent_app_type] => utility
[patent_app_number] => 14/231713
[patent_app_country] => US
[patent_app_date] => 2014-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 33
[patent_no_of_words] => 16376
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231713
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/231713 | Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques | Mar 30, 2014 | Issued |
Array
(
[id] => 10393419
[patent_doc_number] => 20150278426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/228611
[patent_app_country] => US
[patent_app_date] => 2014-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5507
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228611
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/228611 | Metrology pattern layout and method of use thereof | Mar 27, 2014 | Issued |
Array
(
[id] => 12955063
[patent_doc_number] => 09837848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-05
[patent_title] => Foreign-object detection for resonant wireless power system
[patent_app_type] => utility
[patent_app_number] => 14/771568
[patent_app_country] => US
[patent_app_date] => 2014-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 3433
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14771568
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/771568 | Foreign-object detection for resonant wireless power system | Mar 13, 2014 | Issued |
Array
(
[id] => 9599319
[patent_doc_number] => 20140195999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-10
[patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 14/206023
[patent_app_country] => US
[patent_app_date] => 2014-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10170
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206023
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/206023 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT | Mar 11, 2014 | Abandoned |
Array
(
[id] => 11563877
[patent_doc_number] => 09626468
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-18
[patent_title] => 'Assertion extraction from design and its signal traces'
[patent_app_type] => utility
[patent_app_number] => 14/192809
[patent_app_country] => US
[patent_app_date] => 2014-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10732
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192809
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/192809 | Assertion extraction from design and its signal traces | Feb 26, 2014 | Issued |
Array
(
[id] => 9974374
[patent_doc_number] => 09021410
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-04-28
[patent_title] => 'Electronic system with multi-cycle simulation coverage mechanism and method of operation thereof'
[patent_app_type] => utility
[patent_app_number] => 14/182628
[patent_app_country] => US
[patent_app_date] => 2014-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7760
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182628
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/182628 | Electronic system with multi-cycle simulation coverage mechanism and method of operation thereof | Feb 17, 2014 | Issued |
Array
(
[id] => 11220133
[patent_doc_number] => 09448467
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-09-20
[patent_title] => 'Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same'
[patent_app_type] => utility
[patent_app_number] => 14/182859
[patent_app_country] => US
[patent_app_date] => 2014-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 12442
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182859
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/182859 | Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same | Feb 17, 2014 | Issued |
Array
(
[id] => 11220535
[patent_doc_number] => 09448872
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-09-20
[patent_title] => 'Hardware state data logger for silicon debug'
[patent_app_type] => utility
[patent_app_number] => 14/179191
[patent_app_country] => US
[patent_app_date] => 2014-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8518
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179191
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/179191 | Hardware state data logger for silicon debug | Feb 11, 2014 | Issued |
Array
(
[id] => 10328174
[patent_doc_number] => 20150213178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-30
[patent_title] => 'TIER BASED LAYER PROMOTION AND DEMOTION'
[patent_app_type] => utility
[patent_app_number] => 14/166974
[patent_app_country] => US
[patent_app_date] => 2014-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6942
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166974
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/166974 | Tier based layer promotion and demotion | Jan 28, 2014 | Issued |
Array
(
[id] => 10328181
[patent_doc_number] => 20150213185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-30
[patent_title] => 'METHOD, COMPUTER SYSTEM AND COMPUTER-READABLE STORAGE MEDIUM FOR CREATING A LAYOUT OF AN INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 14/166044
[patent_app_country] => US
[patent_app_date] => 2014-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 14298
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166044
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/166044 | Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit | Jan 27, 2014 | Issued |
Array
(
[id] => 11637150
[patent_doc_number] => 09659125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'Computer implemented system and method for generating a layout of a cell defining a circuit component'
[patent_app_type] => utility
[patent_app_number] => 14/165623
[patent_app_country] => US
[patent_app_date] => 2014-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10442
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165623
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/165623 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Jan 27, 2014 | Issued |
Array
(
[id] => 10328168
[patent_doc_number] => 20150213172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-30
[patent_title] => 'METHOD FOR MEASURING AND ANALYZING SURFACE STRUCTURE OF CHIP OR WAFER'
[patent_app_type] => utility
[patent_app_number] => 14/165043
[patent_app_country] => US
[patent_app_date] => 2014-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5022
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165043
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/165043 | Method for measuring and analyzing surface structure of chip or wafer | Jan 26, 2014 | Issued |
Array
(
[id] => 10569468
[patent_doc_number] => 09292638
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-03-22
[patent_title] => 'Method and apparatus for performing timing closure analysis when performing register retiming'
[patent_app_type] => utility
[patent_app_number] => 14/159858
[patent_app_country] => US
[patent_app_date] => 2014-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 8407
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159858
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/159858 | Method and apparatus for performing timing closure analysis when performing register retiming | Jan 20, 2014 | Issued |
Array
(
[id] => 9980640
[patent_doc_number] => 09026971
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-05-05
[patent_title] => 'Multi-patterning conflict free integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 14/148898
[patent_app_country] => US
[patent_app_date] => 2014-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 6332
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148898
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/148898 | Multi-patterning conflict free integrated circuit design | Jan 6, 2014 | Issued |
Array
(
[id] => 10301560
[patent_doc_number] => 20150186560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'SYSTEM FOR AND METHOD OF COMBINING CMOS INVERTERS OF MULTIPLE DRIVE STRENGTHS TO CREATE TUNE-ABLE CLOCK INVERTERS OF VARIABLE DRIVE STRENGTHS IN HYBRID TREE-MESH CLOCK DISTRIBUTION NETWORKS'
[patent_app_type] => utility
[patent_app_number] => 14/141076
[patent_app_country] => US
[patent_app_date] => 2013-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3867
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141076
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/141076 | System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks | Dec 25, 2013 | Issued |