Mohammed Alam

Array ( [id] => 9564064 [patent_doc_number] => 20140181776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'WHAT-IF PARTITIONING AND TIMING' [patent_app_type] => utility [patent_app_number] => 14/140248 [patent_app_country] => US [patent_app_date] => 2013-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571921 [patent_doc_number] => 20140189634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'PRIORI CORNER AND MODE REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/139568 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4887 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9637314 [patent_doc_number] => 20140215423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'SEMICONDUCTOR DEVICE DESIGN METHOD AND DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/132428 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10021581 [patent_doc_number] => 09064069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-23 [patent_title] => 'Creating an end point report based on a comprehensive timing report' [patent_app_type] => utility [patent_app_number] => 14/132068 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9746614 [patent_doc_number] => 20140282333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'DESIGN SUPPORT APPARATUS AND DESIGN SUPPORT METHOD' [patent_app_type] => utility [patent_app_number] => 14/101973 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11262 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9507219 [patent_doc_number] => 08745548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Perturbational technique for co-optimizing design rules and illumination conditions for lithography process' [patent_app_type] => utility [patent_app_number] => 14/102086 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3711 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10218873 [patent_doc_number] => 20150103866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'DIGITAL TEMPERATURE ESTIMATORS (DTEs) DISPOSED IN INTEGRATED CIRCUITS (ICs) FOR ESTIMATING TEMPERATURE WITHIN THE ICs, AND RELATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/091390 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10260483 [patent_doc_number] => 20150145480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'HIGH CAPACITY BATTERIES WITH ON-DEMAND FAST CHARGE CAPABILITY' [patent_app_type] => utility [patent_app_number] => 14/089885 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10264974 [patent_doc_number] => 20150149971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'OPTIMIZING LITHOGRAPHY MASKS FOR VLSI CHIP DESIGN' [patent_app_type] => utility [patent_app_number] => 14/091102 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9768602 [patent_doc_number] => 20140292265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'Active Charge Equilibrium System for Lithium Battery Pack' [patent_app_type] => utility [patent_app_number] => 14/089037 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2413 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9515759 [patent_doc_number] => 20140152251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'APPARATUS AND METHOD FOR CHARGE CONTROL IN WIRELESS CHARGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/089112 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 19595 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9919426 [patent_doc_number] => 20150074631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'DATA ERROR SUSCEPTIBLE BIT IDENTIFICATION' [patent_app_type] => utility [patent_app_number] => 14/089143 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10258329 [patent_doc_number] => 20150143325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MODELING RESISTANCE OF A MULTI-LAYERED CONDUCTIVE COMPONENT' [patent_app_type] => utility [patent_app_number] => 14/084652 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9603108 [patent_doc_number] => 20140199791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'Method and System for Universal Target Based Inspection and Metrology' [patent_app_type] => utility [patent_app_number] => 14/083126 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11292 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9673574 [patent_doc_number] => 20140237437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'LOOK-UP BASED FAST LOGIC SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/068253 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7026 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10236335 [patent_doc_number] => 20150121329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'METHOD AND SYSTEM FOR DESIGNING FIN-FET SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/068064 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9947701 [patent_doc_number] => 08997030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-31 [patent_title] => 'Enhanced case-splitting based property checking' [patent_app_type] => utility [patent_app_number] => 14/064880 [patent_app_country] => US [patent_app_date] => 2013-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7853 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10524784 [patent_doc_number] => 09251300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Methods and tools for designing integrated circuits with auto-pipelining capabilities' [patent_app_type] => utility [patent_app_number] => 14/064031 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6587 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10401757 [patent_doc_number] => 20150286766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'METHOD AND SYSTEM FOR AUTOMATED DESIGN OF AN INTEGRATED CIRCUIT USING CONFIGURABLE CELLS' [patent_app_type] => utility [patent_app_number] => 14/438179 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6944 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9774618 [patent_doc_number] => 20140298281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'METHOD OF GLOBAL DESIGN CLOSURE AT TOP LEVEL AND DRIVING OF DOWNSTREAM IMPLEMENTATION FLOW' [patent_app_type] => utility [patent_app_number] => 14/055653 [patent_app_country] => US [patent_app_date] => 2013-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14055653 [rel_patent_id] =>[rel_patent_doc_number] =>)