
Mohammed Alam
Examiner (ID: 14768, Phone: (571)270-1507 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 1044 |
| Issued Applications | 920 |
| Pending Applications | 67 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9866720
[patent_doc_number] => 20150046739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'REVERSE PERFORMANCE BINNING'
[patent_app_type] => utility
[patent_app_number] => 13/963438
[patent_app_country] => US
[patent_app_date] => 2013-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5040
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963438
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/963438 | Reverse performance binning | Aug 8, 2013 | Issued |
Array
(
[id] => 11884250
[patent_doc_number] => 09755438
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-05
[patent_title] => 'Charging station for electric candles and other devices'
[patent_app_type] => utility
[patent_app_number] => 13/963730
[patent_app_country] => US
[patent_app_date] => 2013-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 6187
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963730
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/963730 | Charging station for electric candles and other devices | Aug 8, 2013 | Issued |
Array
(
[id] => 10577501
[patent_doc_number] => 09300156
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-29
[patent_title] => 'Charge/discharge instructing apparatus and non-transitory computer readable medium'
[patent_app_type] => utility
[patent_app_number] => 13/963222
[patent_app_country] => US
[patent_app_date] => 2013-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 24
[patent_no_of_words] => 10835
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963222
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/963222 | Charge/discharge instructing apparatus and non-transitory computer readable medium | Aug 8, 2013 | Issued |
Array
(
[id] => 9860076
[patent_doc_number] => 20150040093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-05
[patent_title] => 'ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER'
[patent_app_type] => utility
[patent_app_number] => 13/954923
[patent_app_country] => US
[patent_app_date] => 2013-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5768
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954923
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/954923 | Robust numerical optimization for optimizing delay, area, and leakage power | Jul 29, 2013 | Issued |
Array
(
[id] => 10847865
[patent_doc_number] => 08875065
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-28
[patent_title] => 'Triple-pattern lithography layout decomposition validation'
[patent_app_type] => utility
[patent_app_number] => 13/953767
[patent_app_country] => US
[patent_app_date] => 2013-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 24
[patent_no_of_words] => 6803
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953767
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/953767 | Triple-pattern lithography layout decomposition validation | Jul 29, 2013 | Issued |
Array
(
[id] => 9841119
[patent_doc_number] => 20150033201
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-29
[patent_title] => 'SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 13/953532
[patent_app_country] => US
[patent_app_date] => 2013-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8417
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953532
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/953532 | Systems and methods for fabricating semiconductor device structures | Jul 28, 2013 | Issued |
Array
(
[id] => 13651867
[patent_doc_number] => 09852249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-26
[patent_title] => Modified design rules to improve device performance
[patent_app_type] => utility
[patent_app_number] => 13/949683
[patent_app_country] => US
[patent_app_date] => 2013-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 4899
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13949683
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/949683 | Modified design rules to improve device performance | Jul 23, 2013 | Issued |
Array
(
[id] => 9841115
[patent_doc_number] => 20150033197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-29
[patent_title] => 'CLUSTERING FOR PROCESSING OF CIRCUIT DESIGN DATA'
[patent_app_type] => utility
[patent_app_number] => 13/950223
[patent_app_country] => US
[patent_app_date] => 2013-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7242
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950223
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/950223 | Clustering for processing of circuit design data | Jul 23, 2013 | Issued |
Array
(
[id] => 9814704
[patent_doc_number] => 20150026650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-22
[patent_title] => 'INTEGRATED CIRCUIT MANUFACTURE USING DIRECT WRITE LITHOGRAPHY'
[patent_app_type] => utility
[patent_app_number] => 13/944129
[patent_app_country] => US
[patent_app_date] => 2013-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3571
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13944129
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/944129 | Integrated circuit manufacture using direct write lithography | Jul 16, 2013 | Issued |
Array
(
[id] => 10550821
[patent_doc_number] => 09275449
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-01
[patent_title] => 'Methods and systems for determining a dose-to-clear of a photoresist'
[patent_app_type] => utility
[patent_app_number] => 13/943253
[patent_app_country] => US
[patent_app_date] => 2013-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3729
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943253
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/943253 | Methods and systems for determining a dose-to-clear of a photoresist | Jul 15, 2013 | Issued |
Array
(
[id] => 9829457
[patent_doc_number] => 08938696
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-01-20
[patent_title] => 'Techniques of optical proximity correction using GPU'
[patent_app_type] => utility
[patent_app_number] => 13/942395
[patent_app_country] => US
[patent_app_date] => 2013-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 34
[patent_no_of_words] => 30944
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942395
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/942395 | Techniques of optical proximity correction using GPU | Jul 14, 2013 | Issued |
Array
(
[id] => 9808097
[patent_doc_number] => 20150020041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-15
[patent_title] => 'METHOD AND SYSTEM FOR ENHANCED INTEGRATED CIRCUIT LAYOUT'
[patent_app_type] => utility
[patent_app_number] => 13/941196
[patent_app_country] => US
[patent_app_date] => 2013-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4741
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13941196
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/941196 | Method and system for enhanced integrated circuit layout | Jul 11, 2013 | Issued |
Array
(
[id] => 9781484
[patent_doc_number] => 08856708
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-07
[patent_title] => 'Multi-tier field-programmable gate array hardware requirements assessment and verification for airborne electronic systems'
[patent_app_type] => utility
[patent_app_number] => 13/940863
[patent_app_country] => US
[patent_app_date] => 2013-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4095
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13940863
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/940863 | Multi-tier field-programmable gate array hardware requirements assessment and verification for airborne electronic systems | Jul 11, 2013 | Issued |
Array
(
[id] => 9507218
[patent_doc_number] => 08745547
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-06-03
[patent_title] => 'Method for making photomask layout'
[patent_app_type] => utility
[patent_app_number] => 13/940096
[patent_app_country] => US
[patent_app_date] => 2013-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2268
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13940096
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/940096 | Method for making photomask layout | Jul 10, 2013 | Issued |
Array
(
[id] => 10524783
[patent_doc_number] => 09251299
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-02-02
[patent_title] => 'Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs'
[patent_app_type] => utility
[patent_app_number] => 13/931689
[patent_app_country] => US
[patent_app_date] => 2013-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10264
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931689
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/931689 | Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs | Jun 27, 2013 | Issued |
Array
(
[id] => 9420071
[patent_doc_number] => 20140104721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-17
[patent_title] => 'DUMMY HARD DISK DRIVE'
[patent_app_type] => utility
[patent_app_number] => 13/927146
[patent_app_country] => US
[patent_app_date] => 2013-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 687
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927146
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/927146 | DUMMY HARD DISK DRIVE | Jun 25, 2013 | Abandoned |
Array
(
[id] => 11637157
[patent_doc_number] => 09659132
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'Method of generating a target layout on the basis of a source layout'
[patent_app_type] => utility
[patent_app_number] => 14/890961
[patent_app_country] => US
[patent_app_date] => 2013-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 5339
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14890961
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/890961 | Method of generating a target layout on the basis of a source layout | Jun 5, 2013 | Issued |
Array
(
[id] => 9307973
[patent_doc_number] => 20140046647
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'ACTIVE TRACE ASSERTION BASED VERIFICATION SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/910057
[patent_app_country] => US
[patent_app_date] => 2013-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4946
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13910057
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/910057 | Active trace assertion based verification system | Jun 3, 2013 | Issued |
Array
(
[id] => 10841383
[patent_doc_number] => 08869083
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-21
[patent_title] => 'Dynamic bridge generation in package definition systems'
[patent_app_type] => utility
[patent_app_number] => 13/904377
[patent_app_country] => US
[patent_app_date] => 2013-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5104
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13904377
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/904377 | Dynamic bridge generation in package definition systems | May 28, 2013 | Issued |
Array
(
[id] => 9623446
[patent_doc_number] => 08793641
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-07-29
[patent_title] => 'System and method for determining power leakage of electronic circuit design'
[patent_app_type] => utility
[patent_app_number] => 13/902873
[patent_app_country] => US
[patent_app_date] => 2013-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3680
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 343
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13902873
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/902873 | System and method for determining power leakage of electronic circuit design | May 26, 2013 | Issued |