Search

Mohammed Alam

Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1059
Issued Applications
934
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8863722 [patent_doc_number] => 20130147425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'WIRELESS CHARGING SYSTEM AND PORTABLE ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/562300 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1668 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562300 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562300
WIRELESS CHARGING SYSTEM AND PORTABLE ELECTRONIC DEVICE Jul 29, 2012 Abandoned
Array ( [id] => 10103328 [patent_doc_number] => 09139101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Electric/hybrid vehicle charging stands and assembly methods therefor' [patent_app_type] => utility [patent_app_number] => 13/561694 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1146 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561694 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/561694
Electric/hybrid vehicle charging stands and assembly methods therefor Jul 29, 2012 Issued
Array ( [id] => 10112605 [patent_doc_number] => 09148027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Method and system for charging of electric vehicles' [patent_app_type] => utility [patent_app_number] => 13/561393 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9404 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561393 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/561393
Method and system for charging of electric vehicles Jul 29, 2012 Issued
Array ( [id] => 9089549 [patent_doc_number] => 08560997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Conditional cell placement' [patent_app_type] => utility [patent_app_number] => 13/557578 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/557578
Conditional cell placement Jul 24, 2012 Issued
Array ( [id] => 8998277 [patent_doc_number] => 08522183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-27 [patent_title] => 'Static timing analysis adjustments for aging effects' [patent_app_type] => utility [patent_app_number] => 13/539394 [patent_app_country] => US [patent_app_date] => 2012-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539394 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/539394
Static timing analysis adjustments for aging effects Jun 29, 2012 Issued
Array ( [id] => 8805051 [patent_doc_number] => 08443335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Apparatus and method for circuit design' [patent_app_type] => utility [patent_app_number] => 13/481814 [patent_app_country] => US [patent_app_date] => 2012-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9742 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13481814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/481814
Apparatus and method for circuit design May 25, 2012 Issued
Array ( [id] => 8831881 [patent_doc_number] => 20130132926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'COMPUTER AIDED DESIGN SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/471783 [patent_app_country] => US [patent_app_date] => 2012-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13471783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/471783
Computer aided design system and method May 14, 2012 Issued
Array ( [id] => 9150671 [patent_doc_number] => 20130305194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Validation of Integrated Circuit Designs Built With Encrypted Silicon IP Blocks' [patent_app_type] => utility [patent_app_number] => 13/470653 [patent_app_country] => US [patent_app_date] => 2012-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11820 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13470653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/470653
Validation of integrated circuit designs built with encrypted silicon IP blocks May 13, 2012 Issued
Array ( [id] => 8985283 [patent_doc_number] => 08516413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Compilation and simulation of a circuit design' [patent_app_type] => utility [patent_app_number] => 13/468933 [patent_app_country] => US [patent_app_date] => 2012-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13468933 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/468933
Compilation and simulation of a circuit design May 9, 2012 Issued
Array ( [id] => 8474947 [patent_doc_number] => 20120274354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'LOGIC CIRCUIT DESIGN METHOD, LOGIC DESIGN PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/455733 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11882 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455733
Logic circuit design method, logic design program, and semiconductor integrated circuit Apr 24, 2012 Issued
Array ( [id] => 10112202 [patent_doc_number] => 09147620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Edge triggered calibration' [patent_app_type] => utility [patent_app_number] => 13/450123 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450123
Edge triggered calibration Apr 17, 2012 Issued
Array ( [id] => 9404878 [patent_doc_number] => 08694943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness' [patent_app_type] => utility [patent_app_number] => 13/445874 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13569 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445874
Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness Apr 11, 2012 Issued
Array ( [id] => 8672596 [patent_doc_number] => 20130047134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'VIEWING AND DEBUGGING HDL DESIGNS HAVING SYSTEMVERILOG INTERFACE CONSTRUCTS' [patent_app_type] => utility [patent_app_number] => 13/443523 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443523 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443523
Viewing and debugging HDL designs having SystemVerilog interface constructs Apr 9, 2012 Issued
Array ( [id] => 9102874 [patent_doc_number] => 08566768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Best clock frequency search for FPGA-based design' [patent_app_type] => utility [patent_app_number] => 13/441053 [patent_app_country] => US [patent_app_date] => 2012-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5459 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/441053
Best clock frequency search for FPGA-based design Apr 5, 2012 Issued
13/433154 EDGE TRIGGERED CALIBRATION Mar 27, 2012 Abandoned
Array ( [id] => 10100405 [patent_doc_number] => 09136727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Battery charging control device' [patent_app_type] => utility [patent_app_number] => 13/817769 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4541 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13817769 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/817769
Battery charging control device Feb 29, 2012 Issued
Array ( [id] => 8383385 [patent_doc_number] => 20120227015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMINATION CONDITIONS FOR LITHOGRAPHY PROCESS' [patent_app_type] => utility [patent_app_number] => 13/410088 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13410088 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/410088
Perturbational technique for co-optimizing design rules and illumination conditions for lithography process Feb 29, 2012 Issued
Array ( [id] => 8613902 [patent_doc_number] => 20130019214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN DEVICE, THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN, METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/637818 [patent_app_country] => US [patent_app_date] => 2012-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8882 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13637818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/637818
Three-dimensional integrated circuit design device, three-dimensional integrated circuit design, method, and program Feb 16, 2012 Issued
Array ( [id] => 9172063 [patent_doc_number] => 20130314048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'BATTERY DEVICE, BATTERY MANAGEMENT METHOD, AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/984302 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6442 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984302 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/984302
Battery device, battery management method, and electronic apparatus Feb 13, 2012 Issued
Array ( [id] => 8906606 [patent_doc_number] => 20130174109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'DEVICE MISMATCH CORNER MODEL' [patent_app_type] => utility [patent_app_number] => 13/342374 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11231 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342374 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342374
Device mismatch corner model Jan 2, 2012 Issued
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