Search

Mohammed Alam

Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1059
Issued Applications
934
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9714557 [patent_doc_number] => 08839160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Masks for double patterning photolithography' [patent_app_type] => utility [patent_app_number] => 13/977630 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5564 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977630
Masks for double patterning photolithography Dec 28, 2011 Issued
Array ( [id] => 10611468 [patent_doc_number] => 09331515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'System for charging an energy store, and method for operating the charging system' [patent_app_type] => utility [patent_app_number] => 13/984555 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2996 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/984555
System for charging an energy store, and method for operating the charging system Dec 28, 2011 Issued
Array ( [id] => 8998276 [patent_doc_number] => 08522182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Generation of an end point report for a timing simulation of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/314514 [patent_app_country] => US [patent_app_date] => 2011-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13314514 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/314514
Generation of an end point report for a timing simulation of an integrated circuit Dec 7, 2011 Issued
Array ( [id] => 13144195 [patent_doc_number] => 10089432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Rule-check waiver [patent_app_type] => utility [patent_app_number] => 13/304094 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304094
Rule-check waiver Nov 22, 2011 Issued
Array ( [id] => 13144195 [patent_doc_number] => 10089432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Rule-check waiver [patent_app_type] => utility [patent_app_number] => 13/304094 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304094
Rule-check waiver Nov 22, 2011 Issued
Array ( [id] => 9472551 [patent_doc_number] => 08726200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Recognition of template patterns with mask information' [patent_app_type] => utility [patent_app_number] => 13/303374 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13303374 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/303374
Recognition of template patterns with mask information Nov 22, 2011 Issued
Array ( [id] => 9172057 [patent_doc_number] => 20130314042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'Method for Ascertaining the Open Circuit Voltage of a Battery, Battery with a Module for Ascertaining the Open Circuit Voltage and a Motor Vehicle Having a Corresponding Battery' [patent_app_type] => utility [patent_app_number] => 13/990507 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2316 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13990507 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/990507
Method for Ascertaining the Open Circuit Voltage of a Battery, Battery with a Module for Ascertaining the Open Circuit Voltage and a Motor Vehicle Having a Corresponding Battery Nov 20, 2011 Abandoned
Array ( [id] => 9326347 [patent_doc_number] => 08661384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Verification support apparatus, verifying apparatus, computer product, verification support method, and verifying method' [patent_app_type] => utility [patent_app_number] => 13/298354 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 52 [patent_no_of_words] => 18509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298354 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298354
Verification support apparatus, verifying apparatus, computer product, verification support method, and verifying method Nov 16, 2011 Issued
Array ( [id] => 8985299 [patent_doc_number] => 08516429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Circuit optimization method and apparatus for analog circuit migration' [patent_app_type] => utility [patent_app_number] => 13/640594 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5578 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13640594 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/640594
Circuit optimization method and apparatus for analog circuit migration Nov 14, 2011 Issued
Array ( [id] => 8303261 [patent_doc_number] => 20120185814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'INDICATOR CALCULATION METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/280623 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7295 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280623 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280623
Indicator calculation method and apparatus Oct 24, 2011 Issued
Array ( [id] => 8873094 [patent_doc_number] => 08468483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence' [patent_app_type] => utility [patent_app_number] => 13/279373 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13279373 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/279373
Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence Oct 23, 2011 Issued
Array ( [id] => 8765999 [patent_doc_number] => 20130094035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'MULTIPLE PATTERNING TECHNOLOGY METHOD AND SYSTEM FOR ACHIEVING MINIMAL PATTERN MISMATCH' [patent_app_type] => utility [patent_app_number] => 13/275899 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13275899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/275899
Multiple patterning technology method and system for achieving minimal pattern mismatch Oct 17, 2011 Issued
Array ( [id] => 10589221 [patent_doc_number] => 09310831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Multi-mode multi-corner clocktree synthesis' [patent_app_type] => utility [patent_app_number] => 13/274276 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4605 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13274276 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/274276
Multi-mode multi-corner clocktree synthesis Oct 13, 2011 Issued
Array ( [id] => 8757174 [patent_doc_number] => 20130091479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'Parameter Matching Hotspot Detection' [patent_app_type] => utility [patent_app_number] => 13/267874 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5297 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267874
Parameter matching hotspot detection Oct 5, 2011 Issued
Array ( [id] => 8189473 [patent_doc_number] => 20120117518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'DESIGNING SYNTHETIC BIOLOGICAL CIRCUITS USING OPTIMALITY AND NONEQUILIBRIUM THERMODYNAMICS' [patent_app_type] => utility [patent_app_number] => 13/250043 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117518.pdf [firstpage_image] =>[orig_patent_app_number] => 13250043 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/250043
Designing synthetic biological circuits using optimality and nonequilibrium thermodynamics Sep 29, 2011 Issued
Array ( [id] => 9660981 [patent_doc_number] => 08807948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'System and method for automated real-time design checking' [patent_app_type] => utility [patent_app_number] => 13/248914 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9068 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13248914 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/248914
System and method for automated real-time design checking Sep 28, 2011 Issued
Array ( [id] => 8925577 [patent_doc_number] => 20130181337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'Power Routing with Integrated Decoupling Capacitance' [patent_app_type] => utility [patent_app_number] => 13/876303 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3408 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13876303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/876303
Power routing with integrated decoupling capacitance Sep 27, 2011 Issued
Array ( [id] => 9143594 [patent_doc_number] => 08584076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Printed circuit board design assisting device, method, and program' [patent_app_type] => utility [patent_app_number] => 13/238613 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 10900 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238613 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238613
Printed circuit board design assisting device, method, and program Sep 20, 2011 Issued
Array ( [id] => 8935805 [patent_doc_number] => 08495527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Pattern recognition with edge correction for design based metrology' [patent_app_type] => utility [patent_app_number] => 13/236698 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236698
Pattern recognition with edge correction for design based metrology Sep 19, 2011 Issued
Array ( [id] => 8419102 [patent_doc_number] => 20120246602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 13/237663 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237663 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237663
METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT Sep 19, 2011 Abandoned
Menu