Mohammed Alam

Array ( [id] => 8703952 [patent_doc_number] => 08397189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Model checking in state transition machine verification' [patent_app_type] => utility [patent_app_number] => 13/097193 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787185 [patent_doc_number] => 08434040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Clock-reconvergence pessimism removal in hierarchical static timing analysis' [patent_app_type] => utility [patent_app_number] => 13/095713 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5712 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13095713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10879519 [patent_doc_number] => 08904317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Parameter setting circuit and method for integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/093070 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 2664 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7504012 [patent_doc_number] => 20110265048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING UNIFORM OPTICAL PROXIMITY CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/084143 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265048.pdf [firstpage_image] =>[orig_patent_app_number] => 13084143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8889031 [patent_doc_number] => 20130162215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'METHOD AND SYSTEM FOR MANAGING AN ELECTRICAL LOAD OF A USER FACILITY BASED ON LOCALLY MEASURED CONDITIONS OF AN ELECTRICITY SUPPLY GRID' [patent_app_type] => utility [patent_app_number] => 13/639722 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8302 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13639722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8432940 [patent_doc_number] => 20120254816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'NOISE REDUCTION USING FEEDBACK TO A WIRE SPREADER ROUTER' [patent_app_type] => utility [patent_app_number] => 13/078063 [patent_app_country] => US [patent_app_date] => 2011-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13078063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8060461 [patent_doc_number] => 20110246811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD FOR ESTIMATING THE RELIABILITY OF AN ELECTRONIC CIRCUIT, CORRESPONDING COMPUTERIZED SYSTEM AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 13/074204 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17614 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246811.pdf [firstpage_image] =>[orig_patent_app_number] => 13074204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8610507 [patent_doc_number] => 20130015819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'POWER STORAGE UNIT, CORRECTION METHOD FOR CAPACITY VALUES OF STORAGE BATTERIES, AND POWER STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/637449 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9114 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13637449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7653271 [patent_doc_number] => 20110302540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING SHIELD TREE AND RELATED LAYOUT METHOD' [patent_app_type] => utility [patent_app_number] => 13/041804 [patent_app_country] => US [patent_app_date] => 2011-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302540.pdf [firstpage_image] =>[orig_patent_app_number] => 13041804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8382840 [patent_doc_number] => 20120226456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'METHOD OF CALCULATING FET GATE RESISTANCE' [patent_app_type] => utility [patent_app_number] => 13/038460 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10855 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13038460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8372607 [patent_doc_number] => 20120221996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'SYSTEM AND METHOD FOR DISTRIBUTION ANALYSIS OF STACKED-DIE INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/036364 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13036364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8610498 [patent_doc_number] => 20130015809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'DEVICE AND METHOD FOR CONTROLLED EXCHANGE OF ENERGY BETWEEN AN ELECTRICAL POWER NETWORK AND A LOAD' [patent_app_type] => utility [patent_app_number] => 13/637473 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13589 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13637473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8349366 [patent_doc_number] => 20120210289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'WIDE PROCESS RANGE LIBRARY FOR METROLOGY' [patent_app_type] => utility [patent_app_number] => 13/025654 [patent_app_country] => US [patent_app_date] => 2011-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9362 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13025654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8449297 [patent_doc_number] => 08291368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Method for reducing surface area of pad limited semiconductor die layout' [patent_app_type] => utility [patent_app_number] => 13/020814 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13020814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8325988 [patent_doc_number] => 20120198402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'SYSTEMS AND METHODS FOR MAPPING STATE ELEMENTS OF DIGITAL CIRCUITS FOR EQUIVALENCE VERIFICATION' [patent_app_type] => utility [patent_app_number] => 13/015504 [patent_app_country] => US [patent_app_date] => 2011-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4817 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13015504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5960941 [patent_doc_number] => 20110185328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'System and Method for Circuit Design Floorplanning' [patent_app_type] => utility [patent_app_number] => 13/013654 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185328.pdf [firstpage_image] =>[orig_patent_app_number] => 13013654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8574921 [patent_doc_number] => 08341584 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Flexible pin allocation' [patent_app_type] => utility [patent_app_number] => 12/983024 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12983024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9360895 [patent_doc_number] => 20140070767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'CHARGING STATIONS FOR ELECTRIC VEHICLES' [patent_app_type] => utility [patent_app_number] => 13/518847 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13518847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8678843 [patent_doc_number] => 08386980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Integrated circuits design' [patent_app_type] => utility [patent_app_number] => 12/926454 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14897 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12926454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6052613 [patent_doc_number] => 20110209110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'Tensor Transmission-Line Metamaterials' [patent_app_type] => utility [patent_app_number] => 12/945798 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8649 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20110209110.pdf [firstpage_image] =>[orig_patent_app_number] => 12945798 [rel_patent_id] =>[rel_patent_doc_number] =>)