Search

Mohammed Alam

Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1059
Issued Applications
934
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5976985 [patent_doc_number] => 20110154277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING SUBSTRATE LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/642602 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20110154277.pdf [firstpage_image] =>[orig_patent_app_number] => 12642602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/642602
METHOD AND APPARATUS FOR GENERATING SUBSTRATE LAYOUT Dec 17, 2009 Abandoned
Array ( [id] => 6088467 [patent_doc_number] => 20110145780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'Automated Pin Multiplexing for Programmable Logic Device Implementation of Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/638172 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145780.pdf [firstpage_image] =>[orig_patent_app_number] => 12638172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638172
Automated pin multiplexing for programmable logic device implementation of integrated circuit design Dec 14, 2009 Issued
Array ( [id] => 6088465 [patent_doc_number] => 20110145779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'Engineering Change Order Language for Modifying Integrated Circuit Design Files for Programmable Logic Device Implementation' [patent_app_type] => utility [patent_app_number] => 12/638152 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145779.pdf [firstpage_image] =>[orig_patent_app_number] => 12638152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638152
Engineering change order language for modifying integrated circuit design files for programmable logic device implementation Dec 14, 2009 Issued
Array ( [id] => 8540602 [patent_doc_number] => 08316330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'System and method for circuit design automation' [patent_app_type] => utility [patent_app_number] => 12/634192 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8051 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12634192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/634192
System and method for circuit design automation Dec 8, 2009 Issued
Array ( [id] => 8693321 [patent_doc_number] => 08392857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Automated circuit design process for generation of stability constraints for generically defined electronic system with feedback' [patent_app_type] => utility [patent_app_number] => 12/631672 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5598 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12631672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631672
Automated circuit design process for generation of stability constraints for generically defined electronic system with feedback Dec 3, 2009 Issued
Array ( [id] => 6253704 [patent_doc_number] => 20100138802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'PRINTED BOARD DESIGN SYSTEM AND PRINTED BOARD DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/628350 [patent_app_country] => US [patent_app_date] => 2009-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7074 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138802.pdf [firstpage_image] =>[orig_patent_app_number] => 12628350 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/628350
Printed board design system and method including decoupling capacitor arrangement examination unit Nov 30, 2009 Issued
Array ( [id] => 9062993 [patent_doc_number] => 08549448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Delay optimization during circuit design at layout level' [patent_app_type] => utility [patent_app_number] => 12/627470 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12627470 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/627470
Delay optimization during circuit design at layout level Nov 29, 2009 Issued
Array ( [id] => 6241453 [patent_doc_number] => 20100269086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Electron Beam Simulation Corner Correction For Optical Lithpography' [patent_app_type] => utility [patent_app_number] => 12/625466 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9486 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269086.pdf [firstpage_image] =>[orig_patent_app_number] => 12625466 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/625466
Electron beam simulation corner correction for optical lithography Nov 23, 2009 Issued
Array ( [id] => 8985271 [patent_doc_number] => 08516401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Mask model calibration technologies involving etch effect and exposure effect' [patent_app_type] => utility [patent_app_number] => 12/622114 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4118 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12622114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/622114
Mask model calibration technologies involving etch effect and exposure effect Nov 18, 2009 Issued
Array ( [id] => 6057667 [patent_doc_number] => 20110113390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'SMART SELECTION AND/OR WEIGHTING OF PARAMETERS FOR LITHOGRAPHIC PROCESS SIMULATION' [patent_app_type] => utility [patent_app_number] => 12/615004 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7645 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113390.pdf [firstpage_image] =>[orig_patent_app_number] => 12615004 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615004
Smart selection and/or weighting of parameters for lithographic process simulation Nov 8, 2009 Issued
Array ( [id] => 6057667 [patent_doc_number] => 20110113390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'SMART SELECTION AND/OR WEIGHTING OF PARAMETERS FOR LITHOGRAPHIC PROCESS SIMULATION' [patent_app_type] => utility [patent_app_number] => 12/615004 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7645 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113390.pdf [firstpage_image] =>[orig_patent_app_number] => 12615004 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615004
Smart selection and/or weighting of parameters for lithographic process simulation Nov 8, 2009 Issued
Array ( [id] => 6332820 [patent_doc_number] => 20100115485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Circuit design device for conducting failure analysis facilitating design' [patent_app_type] => utility [patent_app_number] => 12/588991 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11062 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20100115485.pdf [firstpage_image] =>[orig_patent_app_number] => 12588991 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588991
Circuit design device for conducting failure analysis facilitating design Nov 3, 2009 Issued
Array ( [id] => 8805036 [patent_doc_number] => 08443319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Method for preparing re-architected designs for sequential equivalence checking' [patent_app_type] => utility [patent_app_number] => 13/128153 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 10939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13128153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/128153
Method for preparing re-architected designs for sequential equivalence checking Oct 27, 2009 Issued
Array ( [id] => 6535232 [patent_doc_number] => 20100218147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING DEVICE, CIRCUIT SPECIFICATION DESCRIPTION VISUALIZING METHOD AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/578659 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20100218147.pdf [firstpage_image] =>[orig_patent_app_number] => 12578659 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/578659
Circuit specification description visualizing device, circuit specification description visualizing method and storage medium Oct 13, 2009 Issued
Array ( [id] => 6513130 [patent_doc_number] => 20100095262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Schematic Generation From Analog Netlists' [patent_app_type] => utility [patent_app_number] => 12/574645 [patent_app_country] => US [patent_app_date] => 2009-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5344 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20100095262.pdf [firstpage_image] =>[orig_patent_app_number] => 12574645 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/574645
Schematic generation visualization aid for netlists comprising analog circuits Oct 5, 2009 Issued
Array ( [id] => 8149415 [patent_doc_number] => 08166433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Method to inspect floating connection and floating net of integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/493425 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2219 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166433.pdf [firstpage_image] =>[orig_patent_app_number] => 12493425 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493425
Method to inspect floating connection and floating net of integrated circuit Jun 28, 2009 Issued
Array ( [id] => 8546515 [patent_doc_number] => 08321818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Model-based retargeting of layout patterns for sub-wavelength photolithography' [patent_app_type] => utility [patent_app_number] => 12/492301 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12492301 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492301
Model-based retargeting of layout patterns for sub-wavelength photolithography Jun 25, 2009 Issued
Array ( [id] => 8536238 [patent_doc_number] => 08312404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages' [patent_app_type] => utility [patent_app_number] => 12/492198 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 8935 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12492198 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492198
Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages Jun 25, 2009 Issued
Array ( [id] => 8366767 [patent_doc_number] => 08255851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Method and system for timing design' [patent_app_type] => utility [patent_app_number] => 12/490758 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7210 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12490758 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/490758
Method and system for timing design Jun 23, 2009 Issued
Array ( [id] => 5466701 [patent_doc_number] => 20090326901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'APPARATUS AND METHOD FOR ESTIMATING CHANGE AMOUNT IN REGISTER TRANSFER LEVEL STRUCTURE AND COMPUTER-READABLE RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/490637 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0326/20090326901.pdf [firstpage_image] =>[orig_patent_app_number] => 12490637 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/490637
APPARATUS AND METHOD FOR ESTIMATING CHANGE AMOUNT IN REGISTER TRANSFER LEVEL STRUCTURE AND COMPUTER-READABLE RECORDING MEDIUM Jun 23, 2009 Abandoned
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