Search

Mohammed Alam

Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1059
Issued Applications
934
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20718502 [patent_doc_number] => 12633765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Method for analyzing the contact assignment of a contact element of a cell module for a vehicle battery and module charger having a diagnosis function for the contact assignment of a contact element [patent_app_type] => utility [patent_app_number] => 17/979865 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979865
Method for analyzing the contact assignment of a contact element of a cell module for a vehicle battery and module charger having a diagnosis function for the contact assignment of a contact element Nov 2, 2022 Issued
Array ( [id] => 20358981 [patent_doc_number] => 12474976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Computation of weakly connected components in a parallel, scalable and deterministic manner [patent_app_type] => utility [patent_app_number] => 17/974412 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/974412
Computation of weakly connected components in a parallel, scalable and deterministic manner Oct 25, 2022 Issued
Array ( [id] => 18228931 [patent_doc_number] => 20230067925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => REDUCED STANDBY CURRENT IN A MULTI-BATTERY WEARABLE DEVICE [patent_app_type] => utility [patent_app_number] => 18/047200 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047200 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047200
Reduced standby current in a multi-battery wearable device Oct 16, 2022 Issued
Array ( [id] => 18438708 [patent_doc_number] => 20230186003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => DIGITAL DESIGN SIMULATION ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/960742 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17960742 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/960742
Digital design simulation accelerator Oct 4, 2022 Issued
Array ( [id] => 18267562 [patent_doc_number] => 20230088804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => LEARNING-BASED ANALYZER FOR MITIGATING LATCH-UP IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/958930 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958930
Learning-based analyzer for mitigating latch-up in integrated circuits Oct 2, 2022 Issued
Array ( [id] => 20494487 [patent_doc_number] => 12536359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Decoupling capacitor parameter determination for a power distribution network [patent_app_type] => utility [patent_app_number] => 17/958249 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2187 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958249
Decoupling capacitor parameter determination for a power distribution network Sep 29, 2022 Issued
Array ( [id] => 18147615 [patent_doc_number] => 20230021472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => METHOD TO AVOID MEMORY BANK CONFLICTS AND PIPELINE CONFLICTS IN TENSOR MEMORY LAYOUT [patent_app_type] => utility [patent_app_number] => 17/954695 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954695
Method to avoid memory bank conflicts and pipeline conflicts in tensor memory layout Sep 27, 2022 Issued
Array ( [id] => 20596679 [patent_doc_number] => 12580406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Optimizing battery charging with synchronized context data [patent_app_type] => utility [patent_app_number] => 17/933712 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9866 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933712
Optimizing battery charging with synchronized context data Sep 19, 2022 Issued
Array ( [id] => 20610253 [patent_doc_number] => 12585855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Method of designing layout of semiconductor integrated circuit, method of designing and manufacturing semiconductor integrated circuit using the same, and design system performing same [patent_app_type] => utility [patent_app_number] => 17/945724 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 8999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945724
Method of designing layout of semiconductor integrated circuit, method of designing and manufacturing semiconductor integrated circuit using the same, and design system performing same Sep 14, 2022 Issued
Array ( [id] => 20298388 [patent_doc_number] => 20250323631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => METHODS AND APPARATUSES RELATING TO HYBRID MULTI-BIT FLIP-FLOPS [patent_app_type] => utility [patent_app_number] => 17/945984 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945984
METHODS AND APPARATUSES RELATING TO HYBRID MULTI-BIT FLIP-FLOPS Sep 14, 2022 Pending
Array ( [id] => 18255964 [patent_doc_number] => 20230083003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => OPTICAL PATH TRACING IN AN OPTICAL CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/942003 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/942003
Optical path tracing in an optical circuit design Sep 8, 2022 Issued
Array ( [id] => 18286500 [patent_doc_number] => 20230101972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATION [patent_app_type] => utility [patent_app_number] => 17/903992 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903992
SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATION Sep 5, 2022 Pending
Array ( [id] => 19006294 [patent_doc_number] => 20240070365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => Backside Contacts for Signal Routing [patent_app_type] => utility [patent_app_number] => 17/823644 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823644
Backside contacts for signal routing Aug 30, 2022 Issued
Array ( [id] => 20373781 [patent_doc_number] => 12481213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Mask corner rounding effects in three-dimensional mask simulations using feature images [patent_app_type] => utility [patent_app_number] => 17/897529 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 3465 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897529
Mask corner rounding effects in three-dimensional mask simulations using feature images Aug 28, 2022 Issued
Array ( [id] => 18648742 [patent_doc_number] => 20230294526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => Electric Vehicles and Charging Stations [patent_app_type] => utility [patent_app_number] => 17/822128 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822128
Electric Vehicles and Charging Stations Aug 23, 2022 Abandoned
Array ( [id] => 20610252 [patent_doc_number] => 12585854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Circuit cells having power grid stubs [patent_app_type] => utility [patent_app_number] => 17/821567 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 10358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821567
Circuit cells having power grid stubs Aug 22, 2022 Issued
Array ( [id] => 20359294 [patent_doc_number] => 12475293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Cell including individual source regions and integrated circuit including the cell [patent_app_type] => utility [patent_app_number] => 17/891760 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891760
Cell including individual source regions and integrated circuit including the cell Aug 18, 2022 Issued
Array ( [id] => 18506648 [patent_doc_number] => 11704466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Routing with soft-penalizing pixels on a found path [patent_app_type] => utility [patent_app_number] => 17/819730 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819730
Routing with soft-penalizing pixels on a found path Aug 14, 2022 Issued
Array ( [id] => 18038741 [patent_doc_number] => 20220382957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SYSTEM FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/885106 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885106
System for generating layout diagram including wiring arrangement Aug 9, 2022 Issued
Array ( [id] => 18196363 [patent_doc_number] => 20230049882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/818080 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818080
Integrated circuit including standard cell and method of designing the integrated circuit Aug 7, 2022 Issued
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