Search

Mohammed Alam

Examiner (ID: 10053, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1042
Issued Applications
920
Pending Applications
65
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20359294 [patent_doc_number] => 12475293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Cell including individual source regions and integrated circuit including the cell [patent_app_type] => utility [patent_app_number] => 17/891760 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891760
Cell including individual source regions and integrated circuit including the cell Aug 18, 2022 Issued
Array ( [id] => 18506648 [patent_doc_number] => 11704466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Routing with soft-penalizing pixels on a found path [patent_app_type] => utility [patent_app_number] => 17/819730 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819730
Routing with soft-penalizing pixels on a found path Aug 14, 2022 Issued
Array ( [id] => 18038741 [patent_doc_number] => 20220382957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SYSTEM FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/885106 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885106
System for generating layout diagram including wiring arrangement Aug 9, 2022 Issued
Array ( [id] => 18196363 [patent_doc_number] => 20230049882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/818080 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818080
Integrated circuit including standard cell and method of designing the integrated circuit Aug 7, 2022 Issued
Array ( [id] => 18856083 [patent_doc_number] => 11853667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Systems and methods for integrated circuit layout [patent_app_type] => utility [patent_app_number] => 17/873840 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873840
Systems and methods for integrated circuit layout Jul 25, 2022 Issued
Array ( [id] => 18942172 [patent_doc_number] => 20240037311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => MULTI-LAYER INTEGRATED CIRCUIT ROUTING TOOL [patent_app_type] => utility [patent_app_number] => 17/814855 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814855 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814855
Multi-layer integrated circuit routing tool Jul 25, 2022 Issued
Array ( [id] => 17962473 [patent_doc_number] => 20220343054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => INTEGRATED CIRCUIT LAYOUT GENERATION METHOD [patent_app_type] => utility [patent_app_number] => 17/860919 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860919
Integrated circuit layout generation method Jul 7, 2022 Issued
Array ( [id] => 18548484 [patent_doc_number] => 11721846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Battery lockout override logic for a battery management system [patent_app_type] => utility [patent_app_number] => 17/851181 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851181
Battery lockout override logic for a battery management system Jun 27, 2022 Issued
Array ( [id] => 18162360 [patent_doc_number] => 20230028953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => IMPLEMENTING FUNCTIONS IN HARDWARE [patent_app_type] => utility [patent_app_number] => 17/848569 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848569
IMPLEMENTING FUNCTIONS IN HARDWARE Jun 23, 2022 Pending
Array ( [id] => 20482043 [patent_doc_number] => 12530518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Length compensating waveguide for an optical circuit [patent_app_type] => utility [patent_app_number] => 17/848614 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848614
Length compensating waveguide for an optical circuit Jun 23, 2022 Issued
Array ( [id] => 19413736 [patent_doc_number] => 12079556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Synchronous FIFO [patent_app_type] => utility [patent_app_number] => 18/564546 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18564546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/564546
Synchronous FIFO Jun 21, 2022 Issued
Array ( [id] => 18728243 [patent_doc_number] => 20230342536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => CAPTURE IR DROP ANALYZER AND ANALYZING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/844083 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844083
Capture IR drop analyzer and analyzing method thereof Jun 19, 2022 Issued
Array ( [id] => 20550708 [patent_doc_number] => 12561502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Finite state machine vulnerability and pipeline analysis using satisfiability modeling [patent_app_type] => utility [patent_app_number] => 17/840163 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840163
Finite state machine vulnerability and pipeline analysis using satisfiability modeling Jun 13, 2022 Issued
Array ( [id] => 18728236 [patent_doc_number] => 20230342529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => CHIP POWER CONSUMPTION ANALYZER AND ANALYZING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/829376 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829376
Chip power consumption analyzer and analyzing method thereof May 31, 2022 Issued
Array ( [id] => 18819872 [patent_doc_number] => 20230394212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => EQUIVALENCE CHECKING OF SYNTHESIZED LOGIC DESIGNS USING GENERATED SYNTHESIS HISTORY [patent_app_type] => utility [patent_app_number] => 17/829811 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829811
Equivalence checking of synthesized logic designs using generated synthesis history May 31, 2022 Issued
Array ( [id] => 18038727 [patent_doc_number] => 20220382943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => IDENTIFYING ASSOCIATION OF SAFETY RELATED PORTS TO THEIR SAFETY MECHANISMS THROUGH STRUCTURAL ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/750809 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750809
Identifying association of safety related ports to their safety mechanisms through structural analysis May 22, 2022 Issued
Array ( [id] => 18728240 [patent_doc_number] => 20230342533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => METHOD FOR INTRA-CELL-REPURPOSING DUMMY TRANSISTORS AND SEMICONDUCTOR DEVICE HAVING REPURPOSED FORMERLY DUMMY TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/743374 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743374
Method for intra-cell-repurposing dummy transistors and semiconductor device having repurposed formerly dummy transistors May 11, 2022 Issued
Array ( [id] => 18333453 [patent_doc_number] => 20230125401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => METHOD OF PREDICTING CHARACTERISTIC OF SEMICONDUCTOR DEVICE AND COMPUTING DEVICE PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/741860 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741860
Method of predicting characteristic of semiconductor device and computing device performing the same May 10, 2022 Issued
Array ( [id] => 20624215 [patent_doc_number] => 12591723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Generating RTL for a circuit using DSP blocks [patent_app_type] => utility [patent_app_number] => 17/739409 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 3377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739409
Generating RTL for a circuit using DSP blocks May 8, 2022 Issued
Array ( [id] => 18639958 [patent_doc_number] => 11764589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => System and method for controlling a high-voltage battery system [patent_app_type] => utility [patent_app_number] => 17/736313 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736313
System and method for controlling a high-voltage battery system May 3, 2022 Issued
Menu