Search

Mohammed Alam

Examiner (ID: 10623, Phone: (571)270-1507 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1059
Issued Applications
934
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18541351 [patent_doc_number] => 20230246467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SYSTEMS AND METHODS FOR PRIORITIZING POWER FLOW BETWEEN ELECTRIFIED VEHICLES AND CHARGING TRAILERS [patent_app_type] => utility [patent_app_number] => 17/590113 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590113
SYSTEMS AND METHODS FOR PRIORITIZING POWER FLOW BETWEEN ELECTRIFIED VEHICLES AND CHARGING TRAILERS Jan 31, 2022 Pending
Array ( [id] => 18539733 [patent_doc_number] => 20230244841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => HIERARCHICAL CDC AND RDC VERIFICATION [patent_app_type] => utility [patent_app_number] => 17/589317 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589317
Hierarchical CDC and RDC verification Jan 30, 2022 Issued
Array ( [id] => 20530595 [patent_doc_number] => 12549038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Shielding system for wireless power transfer [patent_app_type] => utility [patent_app_number] => 17/587261 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 10358 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587261
Shielding system for wireless power transfer Jan 27, 2022 Issued
Array ( [id] => 20115573 [patent_doc_number] => 12365260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Anti-cloning techniques for identifier-based wireless power transfer [patent_app_type] => utility [patent_app_number] => 17/583099 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583099
Anti-cloning techniques for identifier-based wireless power transfer Jan 23, 2022 Issued
Array ( [id] => 18563404 [patent_doc_number] => 11728660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Energy storage apparatus and control method of energy storage devices [patent_app_type] => utility [patent_app_number] => 17/575303 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575303
Energy storage apparatus and control method of energy storage devices Jan 12, 2022 Issued
Array ( [id] => 18386417 [patent_doc_number] => 11657200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Reconfiguration of hardware components of an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/575289 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575289
Reconfiguration of hardware components of an integrated circuit Jan 12, 2022 Issued
Array ( [id] => 18607080 [patent_doc_number] => 11748548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Hierarchical clock tree implementation [patent_app_type] => utility [patent_app_number] => 17/573632 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573632
Hierarchical clock tree implementation Jan 10, 2022 Issued
Array ( [id] => 19856623 [patent_doc_number] => 12259453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Systems and methods for vector-short-open-calibration de-embedding of microwave circuits [patent_app_type] => utility [patent_app_number] => 17/563884 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563884
Systems and methods for vector-short-open-calibration de-embedding of microwave circuits Dec 27, 2021 Issued
Array ( [id] => 19506860 [patent_doc_number] => 12118282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Removal of hardware intellectual property and programmable replacement [patent_app_type] => utility [patent_app_number] => 17/551318 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551318
Removal of hardware intellectual property and programmable replacement Dec 14, 2021 Issued
Array ( [id] => 20203339 [patent_doc_number] => 12406119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Processor chip timing adjustment enhancement [patent_app_type] => utility [patent_app_number] => 17/541797 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541797
Processor chip timing adjustment enhancement Dec 2, 2021 Issued
Array ( [id] => 19523053 [patent_doc_number] => 12124782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-22 [patent_title] => Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis [patent_app_type] => utility [patent_app_number] => 17/516441 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516441
Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis Oct 31, 2021 Issued
Array ( [id] => 18846527 [patent_doc_number] => 20230408931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => METHOD OF DETERMINING MARK STRUCTURE FOR OVERLAY FINGERPRINTS [patent_app_type] => utility [patent_app_number] => 18/035286 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035286 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/035286
METHOD OF DETERMINING MARK STRUCTURE FOR OVERLAY FINGERPRINTS Oct 31, 2021 Pending
Array ( [id] => 18819868 [patent_doc_number] => 20230394208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => DEVICE VERIFICATION METHOD, UVM VERIFICATION PLATFORM, ELECTRONIC APPARATUS AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/259691 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18259691 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/259691
Device verification method, UVM verification platform, electronic apparatus and storage medium Oct 28, 2021 Issued
Array ( [id] => 17546213 [patent_doc_number] => 20220117554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => WIRELESS BATTERY FOR PHYSIOLOGICAL MONITORING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/508440 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508440
Wireless battery for physiological monitoring system Oct 21, 2021 Issued
Array ( [id] => 17598103 [patent_doc_number] => 20220147677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => VERIFICATION OF HARDWARE DESIGN FOR AN INTEGRATED CIRCUIT THAT IMPLEMENTS A FUNCTION THAT IS POLYNOMIAL IN ONE OR MORE SUB-FUNCTIONS [patent_app_type] => utility [patent_app_number] => 17/501666 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501666
Verification of hardware design for an integrated circuit that implements a function that is polynomial in one or more sub-functions Oct 13, 2021 Issued
Array ( [id] => 17535706 [patent_doc_number] => 20220114315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => VERIFICATION OF HARDWARE DESIGN FOR COMPONENT THAT EVALUATES AN ALGEBRAIC EXPRESSION USING DECOMPOSITION AND RECOMBINATION [patent_app_type] => utility [patent_app_number] => 17/501219 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501219
Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination Oct 13, 2021 Issued
Array ( [id] => 18310958 [patent_doc_number] => 20230114858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => CIRCUIT DESIGN SIMULATION AND CLOCK EVENT REDUCTION [patent_app_type] => utility [patent_app_number] => 17/496198 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496198
Circuit design simulation and clock event reduction Oct 6, 2021 Issued
Array ( [id] => 17558204 [patent_doc_number] => 11314913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Information processing apparatus, program, and simulation method [patent_app_type] => utility [patent_app_number] => 17/482924 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4859 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482924
Information processing apparatus, program, and simulation method Sep 22, 2021 Issued
Array ( [id] => 17508062 [patent_doc_number] => 20220101165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CONTROLLABLE QUANTUM LOGIC GATES WITH MEASUREMENT AND METHODS FOR USE THEREWITH [patent_app_type] => utility [patent_app_number] => 17/447848 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447848
Controllable quantum logic gates with measurement and methods for use therewith Sep 15, 2021 Issued
Array ( [id] => 19122688 [patent_doc_number] => 11966677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-23 [patent_title] => Emulation performance analysis using abstract timing graph representation [patent_app_type] => utility [patent_app_number] => 17/462775 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462775
Emulation performance analysis using abstract timing graph representation Aug 30, 2021 Issued
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