Mohammed S Haque
Examiner (ID: 15293)
Most Active Art Unit | 2186 |
Art Unit(s) | 2186 |
Total Applications | 6 |
Issued Applications | 4 |
Pending Applications | 0 |
Abandoned Applications | 2 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6193120
[patent_doc_number] => 20110024874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING A 3D CAPACITOR AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/647621
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2360
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20110024874.pdf
[firstpage_image] =>[orig_patent_app_number] => 12647621
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/647621 | SEMICONDUCTOR DEVICE HAVING A 3D CAPACITOR AND METHOD FOR MANUFACTURING THE SAME | Dec 27, 2009 | Abandoned |
Array
(
[id] => 6393199
[patent_doc_number] => 20100164053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/647639
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6720
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20100164053.pdf
[firstpage_image] =>[orig_patent_app_number] => 12647639
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/647639 | Semiconductor device | Dec 27, 2009 | Issued |
Array
(
[id] => 6153392
[patent_doc_number] => 20110156106
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'HERMETIC MEMS DEVICE AND METHOD FOR FABRICATING HERMETIC MEMS DEVICE AND PACKAGE STRUCTURE OF MEMS DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/647559
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 6860
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20110156106.pdf
[firstpage_image] =>[orig_patent_app_number] => 12647559
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/647559 | Hermetic MEMS device and method for fabricating hermetic MEMS device and package structure of MEMS device | Dec 27, 2009 | Issued |
Array
(
[id] => 6392666
[patent_doc_number] => 20100163938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'METHOD FOR FORMING SILICIDE IN SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/648210
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1534
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20100163938.pdf
[firstpage_image] =>[orig_patent_app_number] => 12648210
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/648210 | METHOD FOR FORMING SILICIDE IN SEMICONDUCTOR DEVICE | Dec 27, 2009 | Abandoned |
Array
(
[id] => 6393182
[patent_doc_number] => 20100164049
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/647694
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2115
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20100164049.pdf
[firstpage_image] =>[orig_patent_app_number] => 12647694
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/647694 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME | Dec 27, 2009 | Abandoned |
Array
(
[id] => 6392751
[patent_doc_number] => 20100163961
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR FLASH MEMORY AND FLASH MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 12/647502
[patent_app_country] => US
[patent_app_date] => 2009-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2442
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20100163961.pdf
[firstpage_image] =>[orig_patent_app_number] => 12647502
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/647502 | Method for manufacturing semiconductor flash memory and flash memory cell | Dec 26, 2009 | Issued |
Array
(
[id] => 6403351
[patent_doc_number] => 20100165681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'SEMICONDUCTOR DEVICE AND POWER CONVERTER USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/646990
[patent_app_country] => US
[patent_app_date] => 2009-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4293
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0165/20100165681.pdf
[firstpage_image] =>[orig_patent_app_number] => 12646990
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/646990 | SEMICONDUCTOR DEVICE AND POWER CONVERTER USING THE SAME | Dec 23, 2009 | Abandoned |
Array
(
[id] => 6153490
[patent_doc_number] => 20110156142
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'HIGH VOLTAGE DEVICE WITH PARTIAL SILICON GERMANIUM EPI SOURCE/DRAIN'
[patent_app_type] => utility
[patent_app_number] => 12/647031
[patent_app_country] => US
[patent_app_date] => 2009-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6024
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20110156142.pdf
[firstpage_image] =>[orig_patent_app_number] => 12647031
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/647031 | High voltage device with partial silicon germanium epi source/drain | Dec 23, 2009 | Issued |
Array
(
[id] => 6457925
[patent_doc_number] => 20100090294
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-15
[patent_title] => 'TAILORING NITROGEN PROFILE IN SILICON OXYNITRIDE USING RAPID THERMAL ANNEALING WITH AMMONIA UNDER ULTRA-LOW PRESSURE'
[patent_app_type] => utility
[patent_app_number] => 12/641064
[patent_app_country] => US
[patent_app_date] => 2009-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6456
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20100090294.pdf
[firstpage_image] =>[orig_patent_app_number] => 12641064
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/641064 | TAILORING NITROGEN PROFILE IN SILICON OXYNITRIDE USING RAPID THERMAL ANNEALING WITH AMMONIA UNDER ULTRA-LOW PRESSURE | Dec 16, 2009 | Abandoned |
Array
(
[id] => 6145404
[patent_doc_number] => 20110018079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-27
[patent_title] => 'APPARATUS AND METHOD OF MANUFACTURE FOR DEPOSITING A COMPOSITE ANTI-REFLECTION LAYER ON A SILICON SURFACE'
[patent_app_type] => utility
[patent_app_number] => 12/632583
[patent_app_country] => US
[patent_app_date] => 2009-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5920
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20110018079.pdf
[firstpage_image] =>[orig_patent_app_number] => 12632583
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/632583 | Apparatus and method of manufacture for depositing a composite anti-reflection layer on a silicon surface | Dec 6, 2009 | Issued |
Array
(
[id] => 6240252
[patent_doc_number] => 20100133639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-03
[patent_title] => 'Photosensitive Semiconductor Component'
[patent_app_type] => utility
[patent_app_number] => 12/624632
[patent_app_country] => US
[patent_app_date] => 2009-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2719
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20100133639.pdf
[firstpage_image] =>[orig_patent_app_number] => 12624632
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624632 | Photosensitive semiconductor component | Nov 23, 2009 | Issued |
Array
(
[id] => 6587019
[patent_doc_number] => 20100047970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-25
[patent_title] => 'INTEGRATED CONDUCTIVE STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/611412
[patent_app_country] => US
[patent_app_date] => 2009-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 16262
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20100047970.pdf
[firstpage_image] =>[orig_patent_app_number] => 12611412
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/611412 | Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system | Nov 2, 2009 | Issued |
Array
(
[id] => 7659330
[patent_doc_number] => 20110308599
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-22
[patent_title] => 'METHOD FOR PRODUCING A WAFER-BASED, REAR-CONTACTED HETERO SOLAR CELLS AND HETERO SOLAR CELL PRODUCED BY THE METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/123739
[patent_app_country] => US
[patent_app_date] => 2009-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4736
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0308/20110308599.pdf
[firstpage_image] =>[orig_patent_app_number] => 13123739
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/123739 | Method for the production of a wafer-based, back-contacted heterojunction solar cell and heterojunction solar cell produced by the method | Oct 9, 2009 | Issued |
Array
(
[id] => 6632169
[patent_doc_number] => 20100035386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines'
[patent_app_type] => utility
[patent_app_number] => 12/588240
[patent_app_country] => US
[patent_app_date] => 2009-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6982
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20100035386.pdf
[firstpage_image] =>[orig_patent_app_number] => 12588240
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/588240 | Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines | Oct 7, 2009 | Issued |
Array
(
[id] => 7750305
[patent_doc_number] => 20120025212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'GeSn Infrared Photodetectors'
[patent_app_type] => utility
[patent_app_number] => 13/062154
[patent_app_country] => US
[patent_app_date] => 2009-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 16653
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0025/20120025212.pdf
[firstpage_image] =>[orig_patent_app_number] => 13062154
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/062154 | GeSn Infrared Photodetectors | Sep 15, 2009 | Abandoned |
Array
(
[id] => 6341163
[patent_doc_number] => 20100020212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'IMAGE PICKUP DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/555854
[patent_app_country] => US
[patent_app_date] => 2009-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6721
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0020/20100020212.pdf
[firstpage_image] =>[orig_patent_app_number] => 12555854
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/555854 | Image pickup device | Sep 8, 2009 | Issued |
Array
(
[id] => 6485904
[patent_doc_number] => 20100009161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-14
[patent_title] => 'STRUCTURE AND METHOD FOR SiCOH INTERFACES WITH INCREASED MECHANICAL STRENGTH'
[patent_app_type] => utility
[patent_app_number] => 12/548487
[patent_app_country] => US
[patent_app_date] => 2009-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5878
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20100009161.pdf
[firstpage_image] =>[orig_patent_app_number] => 12548487
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/548487 | STRUCTURE AND METHOD FOR SiCOH INTERFACES WITH INCREASED MECHANICAL STRENGTH | Aug 26, 2009 | Abandoned |
Array
(
[id] => 4442036
[patent_doc_number] => 07927995
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application'
[patent_app_type] => utility
[patent_app_number] => 12/541502
[patent_app_country] => US
[patent_app_date] => 2009-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 4222
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/927/07927995.pdf
[firstpage_image] =>[orig_patent_app_number] => 12541502
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/541502 | Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application | Aug 13, 2009 | Issued |
Array
(
[id] => 5490451
[patent_doc_number] => 20090291522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'LAYOUT STRUCTURE IN SEMICONDUCTOR MEMORY DEVICE COMPRISING GLOBAL WORD LINES, LOCAL WORD LINES, GLOBAL BIT LINES AND LOCAL BIT LINES'
[patent_app_type] => utility
[patent_app_number] => 12/509617
[patent_app_country] => US
[patent_app_date] => 2009-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7413
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0291/20090291522.pdf
[firstpage_image] =>[orig_patent_app_number] => 12509617
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/509617 | Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit lines and local bit lines | Jul 26, 2009 | Issued |
Array
(
[id] => 5300204
[patent_doc_number] => 20090294856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-03
[patent_title] => 'I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS'
[patent_app_type] => utility
[patent_app_number] => 12/506746
[patent_app_country] => US
[patent_app_date] => 2009-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4295
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0294/20090294856.pdf
[firstpage_image] =>[orig_patent_app_number] => 12506746
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/506746 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process | Jul 20, 2009 | Issued |