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Mohammed S Haque

Examiner (ID: 15293)

Most Active Art Unit
2186
Art Unit(s)
2186
Total Applications
6
Issued Applications
4
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5584544 [patent_doc_number] => 20090103746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'AUDIO ADAPTER HAVING VOLUME ADJUSTING FUNCTION' [patent_app_type] => utility [patent_app_number] => 11/947779 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 884 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103746.pdf [firstpage_image] =>[orig_patent_app_number] => 11947779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947779
AUDIO ADAPTER HAVING VOLUME ADJUSTING FUNCTION Nov 29, 2007 Abandoned
Array ( [id] => 4784552 [patent_doc_number] => 20080137881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 11/947301 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12397 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20080137881.pdf [firstpage_image] =>[orig_patent_app_number] => 11947301 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947301
System and method for digital signal processing Nov 28, 2007 Issued
Array ( [id] => 4675170 [patent_doc_number] => 20080212799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'AUDIO COMPRESSOR WITH FEEDBACK' [patent_app_type] => utility [patent_app_number] => 11/940617 [patent_app_country] => US [patent_app_date] => 2007-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5307 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20080212799.pdf [firstpage_image] =>[orig_patent_app_number] => 11940617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940617
Audio compressor with feedback Nov 14, 2007 Issued
Array ( [id] => 4890690 [patent_doc_number] => 20080099787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 11/873696 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2643 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20080099787.pdf [firstpage_image] =>[orig_patent_app_number] => 11873696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873696
Semiconductor structure and method of manufacture Oct 16, 2007 Issued
Array ( [id] => 5364806 [patent_doc_number] => 20090302365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Nanocrystal Based Universal Memory Cells, And Memory Cells' [patent_app_type] => utility [patent_app_number] => 11/872130 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11940 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302365.pdf [firstpage_image] =>[orig_patent_app_number] => 11872130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/872130
Memory cell comprising dynamic random access memory (DRAM) nanoparticles and nonvolatile memory (NVM) nanoparticle Oct 14, 2007 Issued
Array ( [id] => 4564796 [patent_doc_number] => 07846830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/974389 [patent_app_country] => US [patent_app_date] => 2007-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6961 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/846/07846830.pdf [firstpage_image] =>[orig_patent_app_number] => 11974389 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/974389
Semiconductor device and method for manufacturing same Oct 11, 2007 Issued
Array ( [id] => 4654918 [patent_doc_number] => 20080023778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Fully Silicided Gate Electrodes and Method of Making the Same' [patent_app_type] => utility [patent_app_number] => 11/830312 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4914 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023778.pdf [firstpage_image] =>[orig_patent_app_number] => 11830312 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830312
Fully Silicided Gate Electrodes and Method of Making the Same Jul 29, 2007 Abandoned
Array ( [id] => 5014141 [patent_doc_number] => 20070257349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Leaded Package Integrated Circuit Stacking' [patent_app_type] => utility [patent_app_number] => 11/774846 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20070257349.pdf [firstpage_image] =>[orig_patent_app_number] => 11774846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774846
Leaded Package Integrated Circuit Stacking Jul 8, 2007 Abandoned
Array ( [id] => 5088830 [patent_doc_number] => 20070228469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'THIN-FILM TRANSISTOR FORMED ON INSULATING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/758217 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20070228469.pdf [firstpage_image] =>[orig_patent_app_number] => 11758217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758217
THIN-FILM TRANSISTOR FORMED ON INSULATING SUBSTRATE Jun 4, 2007 Abandoned
Array ( [id] => 5223854 [patent_doc_number] => 20070253120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY' [patent_app_type] => utility [patent_app_number] => 11/737379 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7538 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253120.pdf [firstpage_image] =>[orig_patent_app_number] => 11737379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/737379
MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY Apr 18, 2007 Abandoned
Array ( [id] => 4870770 [patent_doc_number] => 20080197504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'SINGLE-SIDED, FLAT, NO LEAD, INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/697260 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2302 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197504.pdf [firstpage_image] =>[orig_patent_app_number] => 11697260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697260
Single-sided, flat, no lead, integrated circuit package Apr 4, 2007 Issued
Array ( [id] => 75216 [patent_doc_number] => 07750408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit' [patent_app_type] => utility [patent_app_number] => 11/692948 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 13590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/750/07750408.pdf [firstpage_image] =>[orig_patent_app_number] => 11692948 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692948
Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit Mar 28, 2007 Issued
Array ( [id] => 5477 [patent_doc_number] => 07812399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Semiconductor device comprising multi-layer rectangular gate electrode surrounded on four sides by sidewall spacer and implantation regions' [patent_app_type] => utility [patent_app_number] => 11/693408 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 50 [patent_no_of_words] => 16547 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812399.pdf [firstpage_image] =>[orig_patent_app_number] => 11693408 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693408
Semiconductor device comprising multi-layer rectangular gate electrode surrounded on four sides by sidewall spacer and implantation regions Mar 28, 2007 Issued
Array ( [id] => 4715211 [patent_doc_number] => 20080237733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'STRUCTURE AND METHOD TO ENHANCE CHANNEL STRESS BY USING OPTIMIZED STI STRESS AND NITRIDE CAPPING LAYER STRESS' [patent_app_type] => utility [patent_app_number] => 11/691699 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237733.pdf [firstpage_image] =>[orig_patent_app_number] => 11691699 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691699
STRUCTURE AND METHOD TO ENHANCE CHANNEL STRESS BY USING OPTIMIZED STI STRESS AND NITRIDE CAPPING LAYER STRESS Mar 26, 2007 Abandoned
Array ( [id] => 4715371 [patent_doc_number] => 20080237893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Anti Pad To Reduce Parasitic Capacitance And Improve Return Loss In A Semiconductor Die And Package' [patent_app_type] => utility [patent_app_number] => 11/691788 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237893.pdf [firstpage_image] =>[orig_patent_app_number] => 11691788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691788
Anti Pad To Reduce Parasitic Capacitance And Improve Return Loss In A Semiconductor Die And Package Mar 26, 2007 Abandoned
Array ( [id] => 4739713 [patent_doc_number] => 20080233366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'STRUCTURE AND METHOD FOR SiCOH INTERFACES WITH INCREASED MECHANICAL STRENGTH' [patent_app_type] => utility [patent_app_number] => 11/690248 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5836 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233366.pdf [firstpage_image] =>[orig_patent_app_number] => 11690248 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/690248
Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength Mar 22, 2007 Issued
Array ( [id] => 4737196 [patent_doc_number] => 20080230848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD' [patent_app_type] => utility [patent_app_number] => 11/689708 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1845 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20080230848.pdf [firstpage_image] =>[orig_patent_app_number] => 11689708 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689708
STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD Mar 21, 2007 Abandoned
Array ( [id] => 5473 [patent_doc_number] => 07812396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Semiconductor device with channel layer comprising different types of impurities' [patent_app_type] => utility [patent_app_number] => 11/688449 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9883 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812396.pdf [firstpage_image] =>[orig_patent_app_number] => 11688449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688449
Semiconductor device with channel layer comprising different types of impurities Mar 19, 2007 Issued
Array ( [id] => 4915694 [patent_doc_number] => 20080096294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'INTEGRATED CIRCUIT STRUCTURE, DISPLAY MODULE, AND INSPECTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/685149 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2803 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20080096294.pdf [firstpage_image] =>[orig_patent_app_number] => 11685149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685149
INTEGRATED CIRCUIT STRUCTURE, DISPLAY MODULE, AND INSPECTION METHOD THEREOF Mar 11, 2007 Abandoned
Array ( [id] => 4695482 [patent_doc_number] => 20080217666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/683059 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4346 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217666.pdf [firstpage_image] =>[orig_patent_app_number] => 11683059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683059
CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME Mar 6, 2007 Abandoned
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