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Mohammed S Haque

Examiner (ID: 15293)

Most Active Art Unit
2186
Art Unit(s)
2186
Total Applications
6
Issued Applications
4
Pending Applications
0
Abandoned Applications
2

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5685983 [patent_doc_number] => 20060284298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Chip stack package having same length bonding leads' [patent_app_type] => utility [patent_app_number] => 11/302622 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2633 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20060284298.pdf [firstpage_image] =>[orig_patent_app_number] => 11302622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302622
Chip stack package having same length bonding leads Dec 13, 2005 Abandoned
Array ( [id] => 5652781 [patent_doc_number] => 20060138516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Method of forming DRAM device having capacitor and DRAM device so formed' [patent_app_type] => utility [patent_app_number] => 11/301962 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138516.pdf [firstpage_image] =>[orig_patent_app_number] => 11301962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301962
Method of forming DRAM device having capacitor and DRAM device so formed Dec 12, 2005 Issued
Array ( [id] => 5616979 [patent_doc_number] => 20060186511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Monolithically integrated capacitor and method for manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 11/302491 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186511.pdf [firstpage_image] =>[orig_patent_app_number] => 11302491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302491
Monolithically integrated capacitor and method for manufacturing thereof Dec 12, 2005 Abandoned
Array ( [id] => 5805094 [patent_doc_number] => 20060091446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Non-volatile semiconductor memory device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/301736 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091446.pdf [firstpage_image] =>[orig_patent_app_number] => 11301736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301736
Non-volatile semiconductor memory device and its manufacturing method Dec 11, 2005 Abandoned
Array ( [id] => 5647414 [patent_doc_number] => 20060133146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/297392 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10525 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133146.pdf [firstpage_image] =>[orig_patent_app_number] => 11297392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297392
Semiconductor device and a method of manufacturing the same Dec 8, 2005 Abandoned
Array ( [id] => 5838255 [patent_doc_number] => 20060118913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Phase changeable memory cells and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 11/288672 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10565 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118913.pdf [firstpage_image] =>[orig_patent_app_number] => 11288672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288672
Phase changeable memory cells and methods of forming the same Nov 28, 2005 Issued
Array ( [id] => 5810734 [patent_doc_number] => 20060081842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Monitor pattern of semiconductor device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/273294 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 86 [patent_figures_cnt] => 86 [patent_no_of_words] => 17052 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20060081842.pdf [firstpage_image] =>[orig_patent_app_number] => 11273294 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273294
Monitor pattern of semiconductor device and method of manufacturing semiconductor device Nov 14, 2005 Abandoned
Array ( [id] => 5774153 [patent_doc_number] => 20060103025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Semiconductor device including sealing ring' [patent_app_type] => utility [patent_app_number] => 11/271811 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12137 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20060103025.pdf [firstpage_image] =>[orig_patent_app_number] => 11271811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271811
Semiconductor device including sealing ring Nov 13, 2005 Abandoned
Array ( [id] => 5705357 [patent_doc_number] => 20060194405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/266262 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20060194405.pdf [firstpage_image] =>[orig_patent_app_number] => 11266262 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266262
Semiconductor device and method of fabricating the same Nov 3, 2005 Abandoned
Array ( [id] => 911375 [patent_doc_number] => 07329940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-12 [patent_title] => 'Semiconductor structure and method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/163882 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 2601 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/329/07329940.pdf [firstpage_image] =>[orig_patent_app_number] => 11163882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163882
Semiconductor structure and method of manufacture Nov 1, 2005 Issued
Array ( [id] => 5805187 [patent_doc_number] => 20060091540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Semiconductor chip with post-passivation scheme formed over passivation layer' [patent_app_type] => utility [patent_app_number] => 11/262182 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3187 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091540.pdf [firstpage_image] =>[orig_patent_app_number] => 11262182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/262182
Semiconductor chip with passivation layer comprising metal interconnect and contact pads Oct 27, 2005 Issued
Array ( [id] => 7599510 [patent_doc_number] => 07582938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process' [patent_app_type] => utility [patent_app_number] => 11/258253 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/582/07582938.pdf [firstpage_image] =>[orig_patent_app_number] => 11258253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258253
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process Oct 24, 2005 Issued
Array ( [id] => 5732916 [patent_doc_number] => 20060258033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Active matrix substrate and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/254002 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2561 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258033.pdf [firstpage_image] =>[orig_patent_app_number] => 11254002 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254002
Active matrix substrate and method for fabricating the same Oct 18, 2005 Abandoned
Array ( [id] => 5848694 [patent_doc_number] => 20060231906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Structure for measuring gate misalignment and measuring method thereof' [patent_app_type] => utility [patent_app_number] => 11/254081 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5172 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20060231906.pdf [firstpage_image] =>[orig_patent_app_number] => 11254081 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254081
Structure for measuring gate misalignment and measuring method thereof Oct 18, 2005 Abandoned
Array ( [id] => 5191988 [patent_doc_number] => 20070080470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Leaded package integrated circuit stacking' [patent_app_type] => utility [patent_app_number] => 11/248662 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3868 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20070080470.pdf [firstpage_image] =>[orig_patent_app_number] => 11248662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248662
Leaded package integrated circuit stacking Oct 10, 2005 Issued
Array ( [id] => 5718570 [patent_doc_number] => 20060071343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Semiconductor device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/239421 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4113 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071343.pdf [firstpage_image] =>[orig_patent_app_number] => 11239421 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239421
Semiconductor device and method of manufacturing semiconductor device Sep 29, 2005 Abandoned
Array ( [id] => 920165 [patent_doc_number] => 07321172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Selective plating of package terminals' [patent_app_type] => utility [patent_app_number] => 11/227532 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4197 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321172.pdf [firstpage_image] =>[orig_patent_app_number] => 11227532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227532
Selective plating of package terminals Sep 13, 2005 Issued
Array ( [id] => 5611744 [patent_doc_number] => 20060113670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Multi-layer wiring, method of manufacturing the same and thin film transistor having the same' [patent_app_type] => utility [patent_app_number] => 11/221492 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5477 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20060113670.pdf [firstpage_image] =>[orig_patent_app_number] => 11221492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221492
Multi-layer wiring, method of manufacturing the same and thin film transistor having the same Sep 6, 2005 Abandoned
Array ( [id] => 5180765 [patent_doc_number] => 20070052107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'MULTI-LAYERED STRUCTURE AND FABRICATING METHOD THEREOF AND DUAL DAMASCENE STRUCTURE, INTERCONNECT STRUCTURE AND CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/162272 [patent_app_country] => US [patent_app_date] => 2005-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3118 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052107.pdf [firstpage_image] =>[orig_patent_app_number] => 11162272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162272
MULTI-LAYERED STRUCTURE AND FABRICATING METHOD THEREOF AND DUAL DAMASCENE STRUCTURE, INTERCONNECT STRUCTURE AND CAPACITOR Sep 4, 2005 Abandoned
Array ( [id] => 5145795 [patent_doc_number] => 20070045849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Semiconductor structure having selective silicide-induced stress and a method of producing same' [patent_app_type] => utility [patent_app_number] => 11/216512 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045849.pdf [firstpage_image] =>[orig_patent_app_number] => 11216512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216512
Semiconductor structure having selective silicide-induced stress and a method of producing same Aug 30, 2005 Issued
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