Mohammed S Haque
Examiner (ID: 15293)
Most Active Art Unit | 2186 |
Art Unit(s) | 2186 |
Total Applications | 6 |
Issued Applications | 4 |
Pending Applications | 0 |
Abandoned Applications | 2 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5685983
[patent_doc_number] => 20060284298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-21
[patent_title] => 'Chip stack package having same length bonding leads'
[patent_app_type] => utility
[patent_app_number] => 11/302622
[patent_app_country] => US
[patent_app_date] => 2005-12-14
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[pdf_file] => publications/A1/0284/20060284298.pdf
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Array
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[patent_doc_number] => 20060138516
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[patent_issue_date] => 2006-06-29
[patent_title] => 'Method of forming DRAM device having capacitor and DRAM device so formed'
[patent_app_type] => utility
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Array
(
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[patent_doc_number] => 20060186511
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[patent_issue_date] => 2006-08-24
[patent_title] => 'Monolithically integrated capacitor and method for manufacturing thereof'
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[patent_app_number] => 11/302491
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Array
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[patent_title] => 'Non-volatile semiconductor memory device and its manufacturing method'
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Array
(
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[patent_title] => 'Semiconductor device and a method of manufacturing the same'
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Array
(
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[patent_title] => 'Phase changeable memory cells and methods of forming the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/288672 | Phase changeable memory cells and methods of forming the same | Nov 28, 2005 | Issued |
Array
(
[id] => 5810734
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[patent_title] => 'Monitor pattern of semiconductor device and method of manufacturing semiconductor device'
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Array
(
[id] => 5774153
[patent_doc_number] => 20060103025
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[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'Semiconductor device including sealing ring'
[patent_app_type] => utility
[patent_app_number] => 11/271811
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11271811
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/271811 | Semiconductor device including sealing ring | Nov 13, 2005 | Abandoned |
Array
(
[id] => 5705357
[patent_doc_number] => 20060194405
[patent_country] => US
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[patent_title] => 'Semiconductor device and method of fabricating the same'
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Array
(
[id] => 911375
[patent_doc_number] => 07329940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-12
[patent_title] => 'Semiconductor structure and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 11/163882
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[pdf_file] => patents/07/329/07329940.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163882
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163882 | Semiconductor structure and method of manufacture | Nov 1, 2005 | Issued |
Array
(
[id] => 5805187
[patent_doc_number] => 20060091540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Semiconductor chip with post-passivation scheme formed over passivation layer'
[patent_app_type] => utility
[patent_app_number] => 11/262182
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[patent_app_date] => 2005-10-28
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[firstpage_image] =>[orig_patent_app_number] => 11262182
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/262182 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Oct 27, 2005 | Issued |
Array
(
[id] => 7599510
[patent_doc_number] => 07582938
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-01
[patent_title] => 'I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process'
[patent_app_type] => utility
[patent_app_number] => 11/258253
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/258253 | I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process | Oct 24, 2005 | Issued |
Array
(
[id] => 5732916
[patent_doc_number] => 20060258033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Active matrix substrate and method for fabricating the same'
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Array
(
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[patent_title] => 'Structure for measuring gate misalignment and measuring method thereof'
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Array
(
[id] => 5191988
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/248662 | Leaded package integrated circuit stacking | Oct 10, 2005 | Issued |
Array
(
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Array
(
[id] => 920165
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Array
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Array
(
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Array
(
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[patent_title] => 'Semiconductor structure having selective silicide-induced stress and a method of producing same'
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