Mohammed S Haque

Array ( [id] => 17448231 [patent_doc_number] => 20220068736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => INTEGRATED CIRCUIT PACKAGE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/162073 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18402201 [patent_doc_number] => 11664351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Semiconductor package including stacked semiconductor chips [patent_app_type] => utility [patent_app_number] => 17/157648 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 13203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17277963 [patent_doc_number] => 20210384161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/156322 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18688417 [patent_doc_number] => 11784162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Semiconductor package including vertical interconnector [patent_app_type] => utility [patent_app_number] => 17/154705 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9126 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18131354 [patent_doc_number] => 11557571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Stack packages including passive devices [patent_app_type] => utility [patent_app_number] => 17/154797 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6657 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17971397 [patent_doc_number] => 11488946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Package method of a modular stacked semiconductor package [patent_app_type] => utility [patent_app_number] => 17/150498 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 3487 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16873506 [patent_doc_number] => 20210166973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => Method Of Forming Self-Aligned Via [patent_app_type] => utility [patent_app_number] => 17/148982 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18639539 [patent_doc_number] => 11764160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Semiconductor packages including at least one die position checker [patent_app_type] => utility [patent_app_number] => 17/148436 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9028 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18156637 [patent_doc_number] => 11569637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Manufacturable laser diode formed on c-plane gallium and nitrogen material [patent_app_type] => utility [patent_app_number] => 17/143912 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 47 [patent_no_of_words] => 30790 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17247130 [patent_doc_number] => 20210366875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING VERTICAL WIRE BONDS [patent_app_type] => utility [patent_app_number] => 17/137990 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18704783 [patent_doc_number] => 11791300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Electronic package and circuit structure thereof [patent_app_type] => utility [patent_app_number] => 17/135161 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3578 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17690513 [patent_doc_number] => 20220197806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => HIGH SPEED MEMORY SYSTEM INTEGRATION [patent_app_type] => utility [patent_app_number] => 17/133603 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18068377 [patent_doc_number] => 20220399465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => THIN FILM TRANSISTOR, DISPLAY APPARATUS, AND METHOD OF FABRICATING THIN FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/599688 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17599688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17660700 [patent_doc_number] => 20220181165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => Fabrication Method of Flexible Cyclo-Olefin Polymer (COP) Substrate for IC Packaging of Communication Devices and Biocompatible Sensors Devices [patent_app_type] => utility [patent_app_number] => 17/115085 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -50 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16889013 [patent_doc_number] => 20210175210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Three-Dimensional Chip Packaging Structure And Method Thereof [patent_app_type] => utility [patent_app_number] => 17/112835 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16752413 [patent_doc_number] => 20210104425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => ACCOMMODATING DEVICE FOR RETAINING WAFERS [patent_app_type] => utility [patent_app_number] => 17/106402 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17318917 [patent_doc_number] => 20210407967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SLOPED INTERCONNECTOR FOR STACKED DIE PACKAGE [patent_app_type] => utility [patent_app_number] => 17/107838 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16715681 [patent_doc_number] => 20210082828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => ELECTRONIC CIRCUIT DEVICE AND METHOD OF MANUFACTURING ELECTRONIC CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/107806 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17318859 [patent_doc_number] => 20210407909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => INTEGRATED PHOTONICS AND PROCESSOR PACKAGE WITH REDISTRIBUTION LAYER AND EMIB CONNECTOR [patent_app_type] => utility [patent_app_number] => 17/104963 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17630693 [patent_doc_number] => 20220165708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SEMICONDUCTOR ASSEMBLIES WITH HYBRID FANOUTS AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/103486 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103486 [rel_patent_id] =>[rel_patent_doc_number] =>)