Search

Moin M. Rahman

Examiner (ID: 6332, Phone: (571)272-5002 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2898
Total Applications
967
Issued Applications
749
Pending Applications
127
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19422365 [patent_doc_number] => 20240298489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/663715 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663715 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663715
Display device May 13, 2024 Issued
Array ( [id] => 19392884 [patent_doc_number] => 20240282754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => BONDED SEMICONDUCTOR DEVICES HAVING PROCESSOR AND DYNAMIC RANDOM-ACCESS MEMORY AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/648971 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648971
Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same Apr 28, 2024 Issued
Array ( [id] => 19349199 [patent_doc_number] => 20240258163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MITIGATING PATTERN COLLAPSE [patent_app_type] => utility [patent_app_number] => 18/635089 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635089
MITIGATING PATTERN COLLAPSE Apr 14, 2024 Pending
Array ( [id] => 19926444 [patent_doc_number] => 12300740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Metal layer protection during wet etching [patent_app_type] => utility [patent_app_number] => 18/624725 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 2376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624725 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624725
Metal layer protection during wet etching Apr 1, 2024 Issued
Array ( [id] => 19305575 [patent_doc_number] => 20240234155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SINGULATION OF SILICON CARBIDE SEMICONDUCTOR WAFERS [patent_app_type] => utility [patent_app_number] => 18/613913 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613913 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613913
SINGULATION OF SILICON CARBIDE SEMICONDUCTOR WAFERS Mar 21, 2024 Pending
Array ( [id] => 19351298 [patent_doc_number] => 20240260262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => 3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/594804 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594804
3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH MEMORY CELLS Mar 3, 2024 Abandoned
Array ( [id] => 19335716 [patent_doc_number] => 20240250146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHODS FOR MAKING BIPOLAR JUNCTION TRANSISTORS INCLUDING EMITTER-BASE AND BASE-COLLECTOR SUPERLATTICES [patent_app_type] => utility [patent_app_number] => 18/442178 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442178
METHODS FOR MAKING BIPOLAR JUNCTION TRANSISTORS INCLUDING EMITTER-BASE AND BASE-COLLECTOR SUPERLATTICES Feb 14, 2024 Pending
Array ( [id] => 19698512 [patent_doc_number] => 20250017057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/440420 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440420 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440420
DISPLAY DEVICE Feb 12, 2024 Pending
Array ( [id] => 19233508 [patent_doc_number] => 20240190700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/436950 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436950
Semiconductor device and method of manufacturing semiconductor device Feb 7, 2024 Issued
Array ( [id] => 20471016 [patent_doc_number] => 12527062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/430522 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 5456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430522
Semiconductor device Jan 31, 2024 Issued
Array ( [id] => 19285993 [patent_doc_number] => 20240222470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ETCHING PLATINUM-CONTAINING THIN FILM USING PROTECTIVE CAP LAYER [patent_app_type] => utility [patent_app_number] => 18/428198 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428198
ETCHING PLATINUM-CONTAINING THIN FILM USING PROTECTIVE CAP LAYER Jan 30, 2024 Pending
Array ( [id] => 19866389 [patent_doc_number] => 20250105175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SEMICONDUCTOR CHIP INCLUDING CHIP GUARD STRUCTURE AND UPPER GUARD LINE DISPOSED SPACED APART FROM EACH OTHER [patent_app_type] => utility [patent_app_number] => 18/424871 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424871
SEMICONDUCTOR CHIP INCLUDING CHIP GUARD STRUCTURE AND UPPER GUARD LINE DISPOSED SPACED APART FROM EACH OTHER Jan 28, 2024 Pending
Array ( [id] => 20091074 [patent_doc_number] => 20250221010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/424876 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424876
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jan 28, 2024 Pending
Array ( [id] => 20113230 [patent_doc_number] => 12363985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Fluorine-free interface for semiconductor device performance gain [patent_app_type] => utility [patent_app_number] => 18/409119 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409119 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409119
Fluorine-free interface for semiconductor device performance gain Jan 9, 2024 Issued
Array ( [id] => 19148600 [patent_doc_number] => 20240147718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => ANTI-DISHING STRUCTURE FOR EMBEDDED MEMORY [patent_app_type] => utility [patent_app_number] => 18/406592 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406592 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406592
ANTI-DISHING STRUCTURE FOR EMBEDDED MEMORY Jan 7, 2024 Pending
Array ( [id] => 19575621 [patent_doc_number] => 20240379913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/406150 [patent_app_country] => US [patent_app_date] => 2024-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406150
DISPLAY DEVICE Jan 5, 2024 Pending
Array ( [id] => 19875142 [patent_doc_number] => 12268028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Method of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 18/395616 [patent_app_country] => US [patent_app_date] => 2023-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5708 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395616
Method of fabricating semiconductor device Dec 23, 2023 Issued
Array ( [id] => 19688300 [patent_doc_number] => 20250006845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND ARRAY SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/395410 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395410 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395410
THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND ARRAY SUBSTRATE Dec 21, 2023 Pending
Array ( [id] => 19589707 [patent_doc_number] => 20240387264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE [patent_app_type] => utility [patent_app_number] => 18/543532 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543532
ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE Dec 17, 2023 Pending
Array ( [id] => 20055977 [patent_doc_number] => 20250194199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => PITCH CONFIGURATION FOR BACK-END-OF-LINE WIRING [patent_app_type] => utility [patent_app_number] => 18/536918 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536918
PITCH CONFIGURATION FOR BACK-END-OF-LINE WIRING Dec 11, 2023 Pending
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