Molly Kay Reida

Array ( [id] => 12334590 [patent_doc_number] => 09947530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Method of manufacturing nitride semiconductor substrate [patent_app_type] => utility [patent_app_number] => 15/399898 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 6511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12516387 [patent_doc_number] => 10002930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Forming a contact layer on a semiconductor body [patent_app_type] => utility [patent_app_number] => 15/365627 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 4774 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11666134 [patent_doc_number] => 20170154853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'METHOD FOR SINGULATING A MULTIPLICITY OF CHIPS' [patent_app_type] => utility [patent_app_number] => 15/364306 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8474 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11404900 [patent_doc_number] => 20170025438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/283961 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11404900 [patent_doc_number] => 20170025438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/283961 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11404900 [patent_doc_number] => 20170025438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/283961 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11404900 [patent_doc_number] => 20170025438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/283961 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16746452 [patent_doc_number] => 10971453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Semiconductor packaging with high density interconnects [patent_app_type] => utility [patent_app_number] => 16/335845 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16335845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12019645 [patent_doc_number] => 09812355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/280239 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 16235 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11544908 [patent_doc_number] => 20170098733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/279811 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8214 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11687487 [patent_doc_number] => 09685537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-20 [patent_title] => 'Gate length control for vertical transistors and integration with replacement gate flow' [patent_app_type] => utility [patent_app_number] => 15/280521 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3433 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13640521 [patent_doc_number] => 09847221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-19 [patent_title] => Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing [patent_app_type] => utility [patent_app_number] => 15/280049 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13112203 [patent_doc_number] => 10074764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Method of fabricating x-ray absorbers for low-energy x-ray spectroscopy [patent_app_type] => utility [patent_app_number] => 15/280369 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3028 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12595668 [patent_doc_number] => 20180090386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES [patent_app_type] => utility [patent_app_number] => 15/279559 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11593020 [patent_doc_number] => 20170117432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'DAMAGE-AND-RESIST-FREE LASER PATTERNING OF DIELECTRIC FILMS ON TEXTURED SILICON' [patent_app_type] => utility [patent_app_number] => 15/280247 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10498 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12129464 [patent_doc_number] => 20180013050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'METHOD FOR PACKAGING THERMOELECTRIC MODULE' [patent_app_type] => utility [patent_app_number] => 15/280942 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12033800 [patent_doc_number] => 20170323899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => '3D SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/279099 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10196 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12033703 [patent_doc_number] => 20170323803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'METHODS OF ENCAPSULATION' [patent_app_type] => utility [patent_app_number] => 15/279310 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12033687 [patent_doc_number] => 20170323785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'METHOD TO DEPOSIT CONFORMAL AND LOW WET ETCH RATE ENCAPSULATION LAYER USING PECVD' [patent_app_type] => utility [patent_app_number] => 15/279314 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14801581 [patent_doc_number] => 10403802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Method for manufacturing LED display panel [patent_app_type] => utility [patent_app_number] => 15/781056 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6148 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15781056 [rel_patent_id] =>[rel_patent_doc_number] =>)