Search

Molly Kay Reida

Examiner (ID: 13911, Phone: (571)272-4237 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2898, 2899, 2816
Total Applications
651
Issued Applications
507
Pending Applications
82
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11905785 [patent_doc_number] => 09775242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Pin connector structure and method' [patent_app_type] => utility [patent_app_number] => 15/005589 [patent_app_country] => US [patent_app_date] => 2016-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3768 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15005589 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/005589
Pin connector structure and method Jan 24, 2016 Issued
Array ( [id] => 12175172 [patent_doc_number] => 09893320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method for manufacturing light extraction substrate for organic light emitting element, light extraction substrate for organic light emitting element, and organic light emitting element including same' [patent_app_type] => utility [patent_app_number] => 15/540755 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7250 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15540755 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/540755
Method for manufacturing light extraction substrate for organic light emitting element, light extraction substrate for organic light emitting element, and organic light emitting element including same Dec 28, 2015 Issued
Array ( [id] => 12122286 [patent_doc_number] => 20180005872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'PREPARATION OF SILICON-GERMANIUM-ON-INSULATOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/540859 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7576 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15540859 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/540859
PREPARATION OF SILICON-GERMANIUM-ON-INSULATOR STRUCTURES Dec 28, 2015 Abandoned
Array ( [id] => 10765143 [patent_doc_number] => 20160111299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'Methods of Fabricating Tape Film Packages' [patent_app_type] => utility [patent_app_number] => 14/967490 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5363 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967490 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967490
Methods of fabricating tape film packages Dec 13, 2015 Issued
Array ( [id] => 13723895 [patent_doc_number] => 20170372903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => METHOD FOR DOPING SEMICONDUCTORS [patent_app_type] => utility [patent_app_number] => 15/540618 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15540618 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/540618
METHOD FOR DOPING SEMICONDUCTORS Nov 30, 2015 Abandoned
Array ( [id] => 10810658 [patent_doc_number] => 20160156817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'MANUFACTURING METHOD OF IMAGING APPARATUS, IMAGING APPARATUS, AND IMAGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/947961 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947961 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/947961
MANUFACTURING METHOD OF IMAGING APPARATUS, IMAGING APPARATUS, AND IMAGING SYSTEM Nov 19, 2015 Abandoned
Array ( [id] => 10718423 [patent_doc_number] => 20160064571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/939564 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7922 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939564 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939564
Thin film transistor and method of manufacturing the same Nov 11, 2015 Issued
Array ( [id] => 10697051 [patent_doc_number] => 20160043198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SCHOTTKY DIODE WITH BURIED LAYER IN GAN MATERIALS' [patent_app_type] => utility [patent_app_number] => 14/923139 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 8253 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14923139 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/923139
SCHOTTKY DIODE WITH BURIED LAYER IN GAN MATERIALS Oct 25, 2015 Abandoned
Array ( [id] => 12054572 [patent_doc_number] => 20170330916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'COMPLEMENTARY RESISTIVE SWITCHING MEMORY DEVICE HAVING THREE-DIMENSIONAL CROSSBAR-POINT VERTICAL MULTI-LAYER STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/521961 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3472 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15521961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/521961
COMPLEMENTARY RESISTIVE SWITCHING MEMORY DEVICE HAVING THREE-DIMENSIONAL CROSSBAR-POINT VERTICAL MULTI-LAYER STRUCTURE Oct 11, 2015 Abandoned
Array ( [id] => 11831812 [patent_doc_number] => 09728561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-08 [patent_title] => 'Pixel structure for an electronic display' [patent_app_type] => utility [patent_app_number] => 14/869692 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869692 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869692
Pixel structure for an electronic display Sep 28, 2015 Issued
Array ( [id] => 10659680 [patent_doc_number] => 20160005825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/853587 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853587 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853587
Contact structure of semiconductor device Sep 13, 2015 Issued
Array ( [id] => 10993577 [patent_doc_number] => 20160190523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DIODE DISPLAY' [patent_app_type] => utility [patent_app_number] => 14/849371 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849371 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849371
Method of manufacturing organic light-emitting diode display Sep 8, 2015 Issued
Array ( [id] => 11495649 [patent_doc_number] => 20170069834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'Method to Minimize MTJ Sidewall Damage and Bottom Electrode Redeposition Using IBE Trimming' [patent_app_type] => utility [patent_app_number] => 14/848378 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1884 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/848378
Method to minimize MTJ sidewall damage and bottom electrode redeposition using IBE trimming Sep 8, 2015 Issued
Array ( [id] => 13682213 [patent_doc_number] => 20160379843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 14/847582 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847582 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/847582
Method for manufacturing integrated circuit device Sep 7, 2015 Issued
Array ( [id] => 15061273 [patent_doc_number] => 10460948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Stress assisted wet and dry epitaxial lift off [patent_app_type] => utility [patent_app_number] => 14/845346 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3342 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845346 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845346
Stress assisted wet and dry epitaxial lift off Sep 3, 2015 Issued
Array ( [id] => 11495362 [patent_doc_number] => 20170069547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'METHODS OF FORMING CMOS BASED INTEGRATED CIRCUIT PRODUCTS USING DISPOSABLE SPACERS' [patent_app_type] => utility [patent_app_number] => 14/845543 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10583 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845543
Methods of forming CMOS based integrated circuit products using disposable spacers Sep 3, 2015 Issued
Array ( [id] => 10732912 [patent_doc_number] => 20160079062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'PRE-CLEAN OF SILICON GERMANIUM FOR PRE-METAL CONTACT AT SOURCE AND DRAIN AND PRE-HIGH K AT CHANNEL' [patent_app_type] => utility [patent_app_number] => 14/846215 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/846215
Pre-clean of silicon germanium for pre-metal contact at source and drain and pre-high K at channel Sep 3, 2015 Issued
Array ( [id] => 11495343 [patent_doc_number] => 20170069528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'MANUFACTURING METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/845294 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845294
Manufacturing method for forming a semiconductor structure Sep 3, 2015 Issued
Array ( [id] => 10495241 [patent_doc_number] => 20150380264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'ETCH PROCESS WITH PRE-ETCH TRANSIENT CONDITIONING' [patent_app_type] => utility [patent_app_number] => 14/845188 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3638 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845188
Etch process with pre-etch transient conditioning Sep 2, 2015 Issued
Array ( [id] => 11918487 [patent_doc_number] => 09786679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Method for manufacturing semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/844250 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 51 [patent_no_of_words] => 10537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/844250
Method for manufacturing semiconductor memory device Sep 2, 2015 Issued
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