
Molly Kay Reida
Examiner (ID: 11747, Phone: (571)272-4237 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2816, 2898, 2899 |
| Total Applications | 613 |
| Issued Applications | 484 |
| Pending Applications | 84 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11495649
[patent_doc_number] => 20170069834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'Method to Minimize MTJ Sidewall Damage and Bottom Electrode Redeposition Using IBE Trimming'
[patent_app_type] => utility
[patent_app_number] => 14/848378
[patent_app_country] => US
[patent_app_date] => 2015-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1884
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848378
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/848378 | Method to minimize MTJ sidewall damage and bottom electrode redeposition using IBE trimming | Sep 8, 2015 | Issued |
Array
(
[id] => 13682213
[patent_doc_number] => 20160379843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-29
[patent_title] => METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE
[patent_app_type] => utility
[patent_app_number] => 14/847582
[patent_app_country] => US
[patent_app_date] => 2015-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9247
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847582
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/847582 | Method for manufacturing integrated circuit device | Sep 7, 2015 | Issued |
Array
(
[id] => 15061273
[patent_doc_number] => 10460948
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Stress assisted wet and dry epitaxial lift off
[patent_app_type] => utility
[patent_app_number] => 14/845346
[patent_app_country] => US
[patent_app_date] => 2015-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3342
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845346
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/845346 | Stress assisted wet and dry epitaxial lift off | Sep 3, 2015 | Issued |
Array
(
[id] => 10732912
[patent_doc_number] => 20160079062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-17
[patent_title] => 'PRE-CLEAN OF SILICON GERMANIUM FOR PRE-METAL CONTACT AT SOURCE AND DRAIN AND PRE-HIGH K AT CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 14/846215
[patent_app_country] => US
[patent_app_date] => 2015-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7163
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846215
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/846215 | Pre-clean of silicon germanium for pre-metal contact at source and drain and pre-high K at channel | Sep 3, 2015 | Issued |
Array
(
[id] => 11495343
[patent_doc_number] => 20170069528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'MANUFACTURING METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 14/845294
[patent_app_country] => US
[patent_app_date] => 2015-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3528
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845294
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/845294 | Manufacturing method for forming a semiconductor structure | Sep 3, 2015 | Issued |
Array
(
[id] => 11495362
[patent_doc_number] => 20170069547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'METHODS OF FORMING CMOS BASED INTEGRATED CIRCUIT PRODUCTS USING DISPOSABLE SPACERS'
[patent_app_type] => utility
[patent_app_number] => 14/845543
[patent_app_country] => US
[patent_app_date] => 2015-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10583
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845543
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/845543 | Methods of forming CMOS based integrated circuit products using disposable spacers | Sep 3, 2015 | Issued |
Array
(
[id] => 11918487
[patent_doc_number] => 09786679
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-10
[patent_title] => 'Method for manufacturing semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 14/844250
[patent_app_country] => US
[patent_app_date] => 2015-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 51
[patent_no_of_words] => 10537
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844250
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/844250 | Method for manufacturing semiconductor memory device | Sep 2, 2015 | Issued |
Array
(
[id] => 10495241
[patent_doc_number] => 20150380264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'ETCH PROCESS WITH PRE-ETCH TRANSIENT CONDITIONING'
[patent_app_type] => utility
[patent_app_number] => 14/845188
[patent_app_country] => US
[patent_app_date] => 2015-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3638
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845188
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/845188 | Etch process with pre-etch transient conditioning | Sep 2, 2015 | Issued |
Array
(
[id] => 13005981
[patent_doc_number] => 10026661
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-17
[patent_title] => Semiconductor device for testing large number of devices and composing method and test method thereof
[patent_app_type] => utility
[patent_app_number] => 14/844398
[patent_app_country] => US
[patent_app_date] => 2015-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 11749
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844398
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/844398 | Semiconductor device for testing large number of devices and composing method and test method thereof | Sep 2, 2015 | Issued |
Array
(
[id] => 11770267
[patent_doc_number] => 09378959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-28
[patent_title] => 'Method of manufacturing insulated gate transistor semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/844919
[patent_app_country] => US
[patent_app_date] => 2015-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 7871
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 392
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844919
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/844919 | Method of manufacturing insulated gate transistor semiconductor device | Sep 2, 2015 | Issued |
Array
(
[id] => 11861935
[patent_doc_number] => 09741625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-22
[patent_title] => 'Method of forming a semiconductor device with STI structures on an SOI substrate'
[patent_app_type] => utility
[patent_app_number] => 14/844163
[patent_app_country] => US
[patent_app_date] => 2015-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844163
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/844163 | Method of forming a semiconductor device with STI structures on an SOI substrate | Sep 2, 2015 | Issued |
Array
(
[id] => 10725636
[patent_doc_number] => 20160071785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-10
[patent_title] => 'THREE-DIMENSIONAL INTEGRATED CIRCUIT AND TSV REPAIRING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/843638
[patent_app_country] => US
[patent_app_date] => 2015-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3762
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14843638
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/843638 | Three-dimensional integrated circuit and TSV repairing method thereof | Sep 1, 2015 | Issued |
Array
(
[id] => 12396744
[patent_doc_number] => 09966506
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-08
[patent_title] => Light-emission device
[patent_app_type] => utility
[patent_app_number] => 15/516747
[patent_app_country] => US
[patent_app_date] => 2015-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 8275
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15516747
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/516747 | Light-emission device | Aug 25, 2015 | Issued |
Array
(
[id] => 11869622
[patent_doc_number] => 20170236907
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-17
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/521697
[patent_app_country] => US
[patent_app_date] => 2015-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5173
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15521697
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/521697 | Semiconductor device and method for manufacturing the same | Aug 11, 2015 | Issued |
Array
(
[id] => 10787377
[patent_doc_number] => 20160133533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-12
[patent_title] => 'SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 14/816520
[patent_app_country] => US
[patent_app_date] => 2015-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9362
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14816520
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/816520 | Substrate structures and methods of manufacture | Aug 2, 2015 | Issued |
Array
(
[id] => 12115102
[patent_doc_number] => 09871098
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-16
[patent_title] => 'Semiconductor device with suppressed decrease in breakdown voltage of an insulation film and manufacturing method of the same'
[patent_app_type] => utility
[patent_app_number] => 15/516837
[patent_app_country] => US
[patent_app_date] => 2015-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 6992
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15516837
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/516837 | Semiconductor device with suppressed decrease in breakdown voltage of an insulation film and manufacturing method of the same | Jul 21, 2015 | Issued |
Array
(
[id] => 10402636
[patent_doc_number] => 20150287644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/742981
[patent_app_country] => US
[patent_app_date] => 2015-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 58
[patent_no_of_words] => 14096
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742981
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/742981 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | Jun 17, 2015 | Abandoned |
Array
(
[id] => 10604310
[patent_doc_number] => 09324882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-26
[patent_title] => 'Thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 14/721779
[patent_app_country] => US
[patent_app_date] => 2015-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 15065
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721779
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/721779 | Thin film transistor | May 25, 2015 | Issued |
Array
(
[id] => 10604310
[patent_doc_number] => 09324882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-26
[patent_title] => 'Thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 14/721779
[patent_app_country] => US
[patent_app_date] => 2015-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 15065
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721779
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/721779 | Thin film transistor | May 25, 2015 | Issued |
Array
(
[id] => 11599800
[patent_doc_number] => 09646977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-09
[patent_title] => 'Nonvolatile memory device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 14/721970
[patent_app_country] => US
[patent_app_date] => 2015-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 14241
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721970
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/721970 | Nonvolatile memory device and method for fabricating the same | May 25, 2015 | Issued |