Search

Molly Kay Reida

Examiner (ID: 11747, Phone: (571)272-4237 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2898, 2899
Total Applications
613
Issued Applications
484
Pending Applications
84
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17764767 [patent_doc_number] => 20220238380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => LOCALIZED STRESS REGIONS FOR THREE-DIMENSION CHIPLET FORMATION [patent_app_type] => utility [patent_app_number] => 17/486189 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486189
Localized stress regions for three-dimension chiplet formation Sep 26, 2021 Issued
Array ( [id] => 18796939 [patent_doc_number] => 11830774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Buried contact through fin-to-fin space for vertical transport field effect transistor [patent_app_type] => utility [patent_app_number] => 17/482567 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7794 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482567
Buried contact through fin-to-fin space for vertical transport field effect transistor Sep 22, 2021 Issued
Array ( [id] => 18623780 [patent_doc_number] => 11756836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => 3D device layout and method using advanced 3D isolation [patent_app_type] => utility [patent_app_number] => 17/480380 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 60 [patent_no_of_words] => 7931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480380
3D device layout and method using advanced 3D isolation Sep 20, 2021 Issued
Array ( [id] => 18112978 [patent_doc_number] => 20230005858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/480931 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 91449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480931
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME Sep 20, 2021 Pending
Array ( [id] => 18609883 [patent_doc_number] => 11751381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Semiconductor device and fabrication method of the same [patent_app_type] => utility [patent_app_number] => 17/478147 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10693 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478147 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478147
Semiconductor device and fabrication method of the same Sep 16, 2021 Issued
Array ( [id] => 18723322 [patent_doc_number] => 11800700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Memory and its manufacturing method [patent_app_type] => utility [patent_app_number] => 17/476596 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7570 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476596
Memory and its manufacturing method Sep 15, 2021 Issued
Array ( [id] => 18431640 [patent_doc_number] => 11676870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Method of determining thickness of memory gate electrode during device manufacture [patent_app_type] => utility [patent_app_number] => 17/477043 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 7914 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477043
Method of determining thickness of memory gate electrode during device manufacture Sep 15, 2021 Issued
Array ( [id] => 18671871 [patent_doc_number] => 11778804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Capacitor array structure and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/474054 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 6540 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474054 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474054
Capacitor array structure and fabrication method thereof Sep 13, 2021 Issued
Array ( [id] => 18254564 [patent_doc_number] => 20230081603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => THREE TERMINAL PHASE CHANGE MEMORY WITH SELF-ALIGNED CONTACTS [patent_app_type] => utility [patent_app_number] => 17/473359 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473359
Three terminal phase change memory with self-aligned contacts Sep 12, 2021 Issued
Array ( [id] => 19031255 [patent_doc_number] => 11930630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Dynamic random access memory capacitor and preparation method therefor [patent_app_type] => utility [patent_app_number] => 17/471243 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471243 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471243
Dynamic random access memory capacitor and preparation method therefor Sep 9, 2021 Issued
Array ( [id] => 18798670 [patent_doc_number] => 11832538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Resistive memory elements with an embedded heating electrode [patent_app_type] => utility [patent_app_number] => 17/467966 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467966
Resistive memory elements with an embedded heating electrode Sep 6, 2021 Issued
Array ( [id] => 19029926 [patent_doc_number] => 11929290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Method of manufacturing microelectronic components [patent_app_type] => utility [patent_app_number] => 17/446312 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 30 [patent_no_of_words] => 6361 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446312
Method of manufacturing microelectronic components Aug 29, 2021 Issued
Array ( [id] => 18357663 [patent_doc_number] => 11646069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => MRAM semiconductor structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/460348 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5148 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460348
MRAM semiconductor structure and method of forming the same Aug 29, 2021 Issued
Array ( [id] => 17855334 [patent_doc_number] => 20220285377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/459844 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459844
Semiconductor device with regions and contacts Aug 26, 2021 Issued
Array ( [id] => 17870869 [patent_doc_number] => 20220293606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/412992 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412992
Semiconductor memory structure Aug 25, 2021 Issued
Array ( [id] => 17723418 [patent_doc_number] => 20220216140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => INTEGRATED CIRCUIT CAPACITANCE DEVICE AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT CAPACITANCE DEVICE [patent_app_type] => utility [patent_app_number] => 17/445970 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445970
INTEGRATED CIRCUIT CAPACITANCE DEVICE AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT CAPACITANCE DEVICE Aug 25, 2021 Abandoned
Array ( [id] => 18920378 [patent_doc_number] => 11882688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Semiconductor memory device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/403984 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8339 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403984
Semiconductor memory device and method for fabricating the same Aug 16, 2021 Issued
Array ( [id] => 17262859 [patent_doc_number] => 20210375844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => METHOD AND DEVICE FOR MANUFACTURING FLEXIBLE LIGHT EMISSION DEVICE [patent_app_type] => utility [patent_app_number] => 17/403665 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403665
METHOD AND DEVICE FOR MANUFACTURING FLEXIBLE LIGHT EMISSION DEVICE Aug 15, 2021 Abandoned
Array ( [id] => 18198155 [patent_doc_number] => 20230051674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => LOCAL VERTICAL INTERCONNECTS FOR MONOLITHIC STACK TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/445013 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445013
Local vertical interconnects for monolithic stack transistors Aug 12, 2021 Issued
Array ( [id] => 18198565 [patent_doc_number] => 20230052084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/400446 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400446
Semiconductor structure and method for forming the same Aug 11, 2021 Issued
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