Search

Monica D. Harrison

Examiner (ID: 13935, Phone: (571)272-1959 , Office: P/2896 )

Most Active Art Unit
2815
Art Unit(s)
2855, 2896, 2815, 2813, 2829, 2893
Total Applications
1679
Issued Applications
1501
Pending Applications
73
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20252803 [patent_doc_number] => 20250301672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => INTEGRATED MAGNETIC COMPONENT IN ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/614651 [patent_app_country] => US [patent_app_date] => 2024-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614651
INTEGRATED MAGNETIC COMPONENT IN ELECTRONIC APPARATUS Mar 22, 2024 Pending
Array ( [id] => 19285980 [patent_doc_number] => 20240222457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 18/608949 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608949 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608949
Semiconductor structure Mar 18, 2024 Issued
Array ( [id] => 19253065 [patent_doc_number] => 20240204062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/592203 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/592203
SEMICONDUCTOR DEVICE Feb 28, 2024 Pending
Array ( [id] => 19679436 [patent_doc_number] => 12191309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Method to induce strain in finFET channels from an adjacent region [patent_app_type] => utility [patent_app_number] => 18/589774 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 7560 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589774
Method to induce strain in finFET channels from an adjacent region Feb 27, 2024 Issued
Array ( [id] => 20276465 [patent_doc_number] => 12446254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Semiconductor device and methods of forming same [patent_app_type] => utility [patent_app_number] => 18/440071 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 3572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440071
Semiconductor device and methods of forming same Feb 12, 2024 Issued
Array ( [id] => 20002415 [patent_doc_number] => 20250140637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => COOLING MODULE FOR HETEROGENEOUS INTEGRATED SEMICONDUCTOR PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/428130 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428130
COOLING MODULE FOR HETEROGENEOUS INTEGRATED SEMICONDUCTOR PACKAGE STRUCTURE Jan 30, 2024 Pending
Array ( [id] => 19394902 [patent_doc_number] => 20240284772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MANUFACTURING DEVICE OF DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/427817 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427817
MANUFACTURING DEVICE OF DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE Jan 30, 2024 Pending
Array ( [id] => 19436268 [patent_doc_number] => 20240304766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => LIGHT-EMITTING DEVICE PACKAGE AND LIGHTING DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/417508 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417508 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417508
LIGHT-EMITTING DEVICE PACKAGE AND LIGHTING DEVICE INCLUDING THE SAME Jan 18, 2024 Pending
Array ( [id] => 19627233 [patent_doc_number] => 12166084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/412605 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 9277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412605
Semiconductor device and manufacturing method thereof Jan 14, 2024 Issued
Array ( [id] => 19866272 [patent_doc_number] => 20250105058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => FORMING METHOD OF INTERCONNECT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/403751 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403751 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403751
Forming method of interconnect structure Jan 3, 2024 Issued
Array ( [id] => 19218952 [patent_doc_number] => 20240183656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DETECTOR FOR PROCESS KIT RING WEAR [patent_app_type] => utility [patent_app_number] => 18/401881 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401881
DETECTOR FOR PROCESS KIT RING WEAR Jan 1, 2024 Pending
Array ( [id] => 20885991 [patent_doc_number] => 12702051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Integrated circuit packages and methods [patent_app_type] => utility [patent_app_number] => 18/401862 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401862 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401862
INTEGRATED CIRCUIT PACKAGES AND METHODS Jan 1, 2024 Pending
Array ( [id] => 19116609 [patent_doc_number] => 20240128359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/395662 [patent_app_country] => US [patent_app_date] => 2023-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395662
Semiconductor device and manufacturing method Dec 24, 2023 Issued
Array ( [id] => 20072275 [patent_doc_number] => 20250210497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SYSTEMS AND METHODS FOR POWER CONTROL IN 3D STACKED DIE [patent_app_type] => utility [patent_app_number] => 18/395111 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395111
SYSTEMS AND METHODS FOR POWER CONTROL IN 3D STACKED DIE Dec 21, 2023 Pending
Array ( [id] => 19951341 [patent_doc_number] => 12322712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Split source drain transistor [patent_app_type] => utility [patent_app_number] => 18/537236 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 1116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537236
Split source drain transistor Dec 11, 2023 Issued
Array ( [id] => 19766018 [patent_doc_number] => 12224321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Scalable MPS device based on SiC [patent_app_type] => utility [patent_app_number] => 18/532975 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5730 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18532975 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/532975
Scalable MPS device based on SiC Dec 6, 2023 Issued
Array ( [id] => 20705663 [patent_doc_number] => 12628389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Nanosheet FET with controlled overlay mark [patent_app_type] => utility [patent_app_number] => 18/533072 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 5593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533072
Nanosheet FET with controlled overlay mark Dec 6, 2023 Issued
Array ( [id] => 20044942 [patent_doc_number] => 20250183164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => METHODS FOR FORMING THIN FILM RESISTOR [patent_app_type] => utility [patent_app_number] => 18/529008 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529008
METHODS FOR FORMING THIN FILM RESISTOR Dec 4, 2023 Pending
Array ( [id] => 19086311 [patent_doc_number] => 20240113112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => Semiconductor Structure Cutting Process and Structures Formed Thereby [patent_app_type] => utility [patent_app_number] => 18/526062 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526062 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526062
Semiconductor structure cutting process and structures formed thereby Nov 30, 2023 Issued
Array ( [id] => 19054974 [patent_doc_number] => 20240096943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => REDUCING PARASITIC CAPACITANCE IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/520346 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520346 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520346
Reducing parasitic capacitance in semiconductor devices Nov 26, 2023 Issued
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