Search

Monjur Rahim

Examiner (ID: 13026, Phone: (571)270-3890 , Office: P/2436 )

Most Active Art Unit
2436
Art Unit(s)
2492, 2434, 2134, 2436
Total Applications
1026
Issued Applications
835
Pending Applications
72
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12114447 [patent_doc_number] => 09870441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-16 [patent_title] => 'Snap-to valid pattern system and method' [patent_app_type] => utility [patent_app_number] => 15/073493 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2173 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073493
Snap-to valid pattern system and method Mar 16, 2016 Issued
Array ( [id] => 10991829 [patent_doc_number] => 20160188774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'Circuit Design and Optimization' [patent_app_type] => utility [patent_app_number] => 15/063479 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063479 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063479
Circuit Design and Optimization Mar 6, 2016 Abandoned
Array ( [id] => 10991840 [patent_doc_number] => 20160188786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'TECHNOLOGY FOR TEMPERATURE SENSITIVE COMPONENTS IN THERMAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/062196 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062196 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062196
Technology for temperature sensitive components in thermal processing Mar 6, 2016 Issued
Array ( [id] => 10809545 [patent_doc_number] => 20160155704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL' [patent_app_type] => utility [patent_app_number] => 15/016448 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016448
Different scaling ratio in FEOL/ MOL/ BEOL Feb 4, 2016 Issued
Array ( [id] => 12937354 [patent_doc_number] => 09831700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Mitigating premature wear out of a rechargeable battery [patent_app_type] => utility [patent_app_number] => 14/993013 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993013 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993013
Mitigating premature wear out of a rechargeable battery Jan 10, 2016 Issued
Array ( [id] => 11078249 [patent_doc_number] => 20160275213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'BEHAVIORAL SYNTHESIS METHOD, BEHAVIORAL SYNTHESIS DEVICE AND COMPUTER READABLE RECORDING MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/990292 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990292
BEHAVIORAL SYNTHESIS METHOD, BEHAVIORAL SYNTHESIS DEVICE AND COMPUTER READABLE RECORDING MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM Jan 6, 2016 Abandoned
Array ( [id] => 11745884 [patent_doc_number] => 20170199957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'METHOD OF DETERMINING COLORABILITY OF A SEMICONDUCTOR DEVICE AND SYSTEM FOR IMPLEMENTING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/990446 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990446 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990446
Method of determining colorability of a semiconductor device and system for implementing the same Jan 6, 2016 Issued
Array ( [id] => 13918965 [patent_doc_number] => 10203596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Method of filtering overlay data by field [patent_app_type] => utility [patent_app_number] => 14/989765 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2943 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989765 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989765
Method of filtering overlay data by field Jan 5, 2016 Issued
Array ( [id] => 14150043 [patent_doc_number] => 10255403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-09 [patent_title] => Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs [patent_app_type] => utility [patent_app_number] => 14/988808 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14988808 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/988808
Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs Jan 5, 2016 Issued
Array ( [id] => 15059525 [patent_doc_number] => 10460069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Functional reactive PCells [patent_app_type] => utility [patent_app_number] => 14/984844 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984844 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984844
Functional reactive PCells Dec 29, 2015 Issued
Array ( [id] => 10983070 [patent_doc_number] => 20160180014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'ENHANCING INTEGRATED CIRCUIT NOISE PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/967433 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967433
Enhancing integrated circuit noise performance Dec 13, 2015 Issued
Array ( [id] => 11693437 [patent_doc_number] => 20170169154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SYSTEM AND METHOD FOR MULTI-PATTERNING' [patent_app_type] => utility [patent_app_number] => 14/967061 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967061 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967061
System and method for multi-patterning Dec 10, 2015 Issued
Array ( [id] => 11692671 [patent_doc_number] => 20170168386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'STRUCTURE DESIGN GENERATION FOR FIXING METAL TIP-TO-TIP ACROSS CELL BOUNDARY' [patent_app_type] => utility [patent_app_number] => 14/967103 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967103 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967103
Structure design generation for fixing metal tip-to-tip across cell boundary Dec 10, 2015 Issued
Array ( [id] => 11693440 [patent_doc_number] => 20170169157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'BUILDING A CORNER MODEL OF INTERCONNECT WIRE RESISTANCE' [patent_app_type] => utility [patent_app_number] => 14/967140 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967140 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967140
Building a corner model of interconnect wire resistance Dec 10, 2015 Issued
Array ( [id] => 10983058 [patent_doc_number] => 20160180002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR GENERATING SEMICONDUCTOR CIRCUIT LAYOUTS' [patent_app_type] => utility [patent_app_number] => 14/966264 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9809 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14966264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/966264
Methods, systems, and computer program products for generating semiconductor circuit layouts Dec 10, 2015 Issued
Array ( [id] => 11693434 [patent_doc_number] => 20170169151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHODS AND COMPUTER PROGRAM PRODUCTS FOR VIA CAPACITANCE EXTRACTION' [patent_app_type] => utility [patent_app_number] => 14/964863 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964863 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/964863
Methods and computer program products for via capacitance extraction Dec 9, 2015 Issued
Array ( [id] => 11693438 [patent_doc_number] => 20170169155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHOD TO ADJUST ALLEY GAP BETWEEN LARGE BLOCKS FOR FLOORPLAN OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/964813 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964813 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/964813
METHOD TO ADJUST ALLEY GAP BETWEEN LARGE BLOCKS FOR FLOORPLAN OPTIMIZATION Dec 9, 2015 Abandoned
Array ( [id] => 11077220 [patent_doc_number] => 20160274184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'SEMICONDUCTOR APPARATUS AND DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/964362 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964362 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/964362
Semiconductor apparatus and design apparatus Dec 8, 2015 Issued
Array ( [id] => 11077220 [patent_doc_number] => 20160274184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'SEMICONDUCTOR APPARATUS AND DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/964362 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964362 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/964362
Semiconductor apparatus and design apparatus Dec 8, 2015 Issued
Array ( [id] => 12497808 [patent_doc_number] => 09997225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => System and method for modular simulation of spin transfer torque magnetic random access memory devices [patent_app_type] => utility [patent_app_number] => 14/963264 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 11285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963264
System and method for modular simulation of spin transfer torque magnetic random access memory devices Dec 8, 2015 Issued
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