Search

Monjur Rahim

Examiner (ID: 13026, Phone: (571)270-3890 , Office: P/2436 )

Most Active Art Unit
2436
Art Unit(s)
2492, 2434, 2134, 2436
Total Applications
1026
Issued Applications
835
Pending Applications
72
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11687761 [patent_doc_number] => 09685813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Radio communication apparatus, radio communication system, and radio communication control method' [patent_app_type] => utility [patent_app_number] => 14/083519 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6298 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083519 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/083519
Radio communication apparatus, radio communication system, and radio communication control method Nov 18, 2013 Issued
Array ( [id] => 10258322 [patent_doc_number] => 20150143319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL' [patent_app_type] => utility [patent_app_number] => 14/082487 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082487
Different scaling ratio in FEOL / MOL/ BEOL Nov 17, 2013 Issued
Array ( [id] => 10258307 [patent_doc_number] => 20150143304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'Target Point Generation for Optical Proximity Correction' [patent_app_type] => utility [patent_app_number] => 14/081521 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/081521
Target point generation for optical proximity correction Nov 14, 2013 Issued
Array ( [id] => 10231001 [patent_doc_number] => 20150115994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY' [patent_app_type] => utility [patent_app_number] => 14/064337 [patent_app_country] => US [patent_app_date] => 2013-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064337
Optimization of integrated circuit reliability Oct 27, 2013 Issued
Array ( [id] => 9320782 [patent_doc_number] => 20140053120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/064067 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12895 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064067
Architectural physical synthesis Oct 24, 2013 Issued
Array ( [id] => 9386395 [patent_doc_number] => 20140089878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'DETERMINING APPARATUS, DETERMINING METHOD, AND COMPUTER PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/031241 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11100 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14031241 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/031241
DETERMINING APPARATUS, DETERMINING METHOD, AND COMPUTER PRODUCT Sep 18, 2013 Abandoned
Array ( [id] => 9665995 [patent_doc_number] => 08813005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-19 [patent_title] => 'Debugging using tagged flip-flops' [patent_app_type] => utility [patent_app_number] => 14/016941 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5860 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016941 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016941
Debugging using tagged flip-flops Sep 2, 2013 Issued
Array ( [id] => 9265003 [patent_doc_number] => 20130346932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI' [patent_app_type] => utility [patent_app_number] => 14/010842 [patent_app_country] => US [patent_app_date] => 2013-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5941 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010842 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/010842
Intelligent timing analysis and constraint generation GUI Aug 26, 2013 Issued
Array ( [id] => 9695574 [patent_doc_number] => 08826205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Method for verifying digital to analog converter design' [patent_app_type] => utility [patent_app_number] => 13/965201 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3133 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965201 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965201
Method for verifying digital to analog converter design Aug 12, 2013 Issued
Array ( [id] => 9866869 [patent_doc_number] => 20150046888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'MASK DESIGN AND DECOMPOSITION FOR SIDEWALL IMAGE TRANSFER' [patent_app_type] => utility [patent_app_number] => 13/960873 [patent_app_country] => US [patent_app_date] => 2013-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960873 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/960873
Mask design and decomposition for sidewall image transfer Aug 6, 2013 Issued
Array ( [id] => 10847883 [patent_doc_number] => 08875084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-28 [patent_title] => 'Optimal spare latch selection for metal-only ECOs' [patent_app_type] => utility [patent_app_number] => 13/945191 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5456 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/945191
Optimal spare latch selection for metal-only ECOs Jul 17, 2013 Issued
Array ( [id] => 12352833 [patent_doc_number] => 09953120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Relative timing characterization [patent_app_type] => utility [patent_app_number] => 13/945775 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 38 [patent_no_of_words] => 16676 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945775 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/945775
Relative timing characterization Jul 17, 2013 Issued
Array ( [id] => 9800951 [patent_doc_number] => 20150012896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING GENERATING PHOTOMASKS FOR DIRECTED SELF-ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 13/936910 [patent_app_country] => US [patent_app_date] => 2013-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936910 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/936910
Methods for fabricating integrated circuits including generating photomasks for directed self-assembly Jul 7, 2013 Issued
Array ( [id] => 9271191 [patent_doc_number] => 20140026109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR AUTOMATICALLY CHECKING WIRING INFORMATION' [patent_app_type] => utility [patent_app_number] => 13/928797 [patent_app_country] => US [patent_app_date] => 2013-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1705 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928797 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/928797
Computing device and method for automatically checking wiring information Jun 26, 2013 Issued
Array ( [id] => 11749853 [patent_doc_number] => 09707854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Series booster pack for battery system capacity recovery' [patent_app_type] => utility [patent_app_number] => 13/920224 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6390 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13920224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/920224
Series booster pack for battery system capacity recovery Jun 17, 2013 Issued
Array ( [id] => 9891730 [patent_doc_number] => 08978005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Network reconfiguration in a data converter for improved electrical characteristics' [patent_app_type] => utility [patent_app_number] => 13/911720 [patent_app_country] => US [patent_app_date] => 2013-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7902 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13911720 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/911720
Network reconfiguration in a data converter for improved electrical characteristics Jun 5, 2013 Issued
Array ( [id] => 11897305 [patent_doc_number] => 09767242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Filling vacant areas of an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 13/909872 [patent_app_country] => US [patent_app_date] => 2013-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9346 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13909872 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/909872
Filling vacant areas of an integrated circuit design Jun 3, 2013 Issued
Array ( [id] => 10873379 [patent_doc_number] => 08898599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Gradient-based pattern and evaluation point selection' [patent_app_type] => utility [patent_app_number] => 13/904867 [patent_app_country] => US [patent_app_date] => 2013-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 19582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13904867 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/904867
Gradient-based pattern and evaluation point selection May 28, 2013 Issued
Array ( [id] => 9695569 [patent_doc_number] => 08826200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Alteration for wafer inspection' [patent_app_type] => utility [patent_app_number] => 13/893267 [patent_app_country] => US [patent_app_date] => 2013-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8786 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893267 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893267
Alteration for wafer inspection May 12, 2013 Issued
Array ( [id] => 9150683 [patent_doc_number] => 20130305206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Measurement Model Optimization Based On Parameter Variations Across A Wafer' [patent_app_type] => utility [patent_app_number] => 13/887357 [patent_app_country] => US [patent_app_date] => 2013-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13887357 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/887357
Measurement model optimization based on parameter variations across a wafer May 4, 2013 Issued
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