Search

Monjur Rahim

Examiner (ID: 13026, Phone: (571)270-3890 , Office: P/2436 )

Most Active Art Unit
2436
Art Unit(s)
2492, 2434, 2134, 2436
Total Applications
1026
Issued Applications
835
Pending Applications
72
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9654560 [patent_doc_number] => 20140225565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING ELECTRICAL ENERGY' [patent_app_type] => utility [patent_app_number] => 14/239590 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9521 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14239590 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/239590
Method and apparatus for providing electrical energy Aug 18, 2011 Issued
Array ( [id] => 7808545 [patent_doc_number] => 20120059499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'DESIGN AIDING DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM IN WHICH DESIGN AIDING PROGRAM IS STORED' [patent_app_type] => utility [patent_app_number] => 13/211457 [patent_app_country] => US [patent_app_date] => 2011-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11330 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20120059499.pdf [firstpage_image] =>[orig_patent_app_number] => 13211457 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/211457
Aiding device, and non-transitory computer-readable recording medium in which design aiding program is stored Aug 16, 2011 Issued
Array ( [id] => 9404866 [patent_doc_number] => 08694930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Method and apparatus for providing a layout defining a structure to be patterned onto a substrate' [patent_app_type] => utility [patent_app_number] => 13/208237 [patent_app_country] => US [patent_app_date] => 2011-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7151 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13208237 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/208237
Method and apparatus for providing a layout defining a structure to be patterned onto a substrate Aug 10, 2011 Issued
Array ( [id] => 9431142 [patent_doc_number] => 08707229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Static analysis of VLSI reliability' [patent_app_type] => utility [patent_app_number] => 13/191487 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7693 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191487 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/191487
Static analysis of VLSI reliability Jul 26, 2011 Issued
Array ( [id] => 10513116 [patent_doc_number] => 09240696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-19 [patent_title] => 'Method and apparatus for recharging a battery' [patent_app_type] => utility [patent_app_number] => 13/810003 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 29126 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13810003 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/810003
Method and apparatus for recharging a battery Jul 14, 2011 Issued
Array ( [id] => 7504011 [patent_doc_number] => 20110265047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Mask data processing method for optimizing hierarchical structure' [patent_app_type] => utility [patent_app_number] => 13/067810 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7292 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265047.pdf [firstpage_image] =>[orig_patent_app_number] => 13067810 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067810
Mask data processing method for optimizing hierarchical structure Jun 27, 2011 Abandoned
Array ( [id] => 8485273 [patent_doc_number] => 20120284680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/116557 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/116557
Method and apparatus for designing an integrated circuit May 25, 2011 Issued
Array ( [id] => 8485269 [patent_doc_number] => 20120284676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/099767 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6063 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13099767 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/099767
Decoupling capacitor insertion using hypergraph connectivity analysis May 2, 2011 Issued
Array ( [id] => 9023646 [patent_doc_number] => 08533645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Reducing narrow gate width effects in an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 13/097537 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4514 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/097537
Reducing narrow gate width effects in an integrated circuit design Apr 28, 2011 Issued
Array ( [id] => 10162054 [patent_doc_number] => 09193269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Vehicle charger mounting structure' [patent_app_type] => utility [patent_app_number] => 13/701248 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3047 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13701248 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/701248
Vehicle charger mounting structure Apr 26, 2011 Issued
Array ( [id] => 9214117 [patent_doc_number] => 20140013294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN AND CORRESPONDING COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/003361 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14003361 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/003361
Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product Mar 27, 2011 Issued
Array ( [id] => 8695195 [patent_doc_number] => 20130057204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'SYSTEM AND METHOD FOR TRANSFERRING ELECTRIC ENERGY TO A VEHICLE' [patent_app_type] => utility [patent_app_number] => 13/517350 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6931 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13517350 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/517350
SYSTEM AND METHOD FOR TRANSFERRING ELECTRIC ENERGY TO A VEHICLE Dec 20, 2010 Abandoned
Array ( [id] => 8851367 [patent_doc_number] => 20130141042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'METHOD FOR CHARGING A RECHARGEABLE ENERGY STORE, CHARGING DEVICE FOR A RECHARGEABLE ENERGY STORE, AND CIRCUIT BREAKER' [patent_app_type] => utility [patent_app_number] => 13/577683 [patent_app_country] => US [patent_app_date] => 2010-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5675 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13577683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/577683
Method for charging a rechargeable energy store, charging device for a rechargeable energy store, and circuit breaker Dec 19, 2010 Issued
Array ( [id] => 9187254 [patent_doc_number] => 08627255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Methods and systems for flexible and repeatable pre-route generation' [patent_app_type] => utility [patent_app_number] => 12/916317 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7067 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12916317 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/916317
Methods and systems for flexible and repeatable pre-route generation Oct 28, 2010 Issued
Array ( [id] => 10873384 [patent_doc_number] => 08898605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'On-chip tunable transmission lines, methods of manufacture and design structures' [patent_app_type] => utility [patent_app_number] => 12/911327 [patent_app_country] => US [patent_app_date] => 2010-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12911327 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/911327
On-chip tunable transmission lines, methods of manufacture and design structures Oct 24, 2010 Issued
Array ( [id] => 8162780 [patent_doc_number] => 20120102445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'IMPLEMENTING ENHANCED RLM CONNECTIVITY ON A HIERARCHICAL DESIGN WITH TOP LEVEL PIPELINE REGISTERS' [patent_app_type] => utility [patent_app_number] => 12/910127 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2043 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102445.pdf [firstpage_image] =>[orig_patent_app_number] => 12910127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/910127
Implementing enhanced RLM connectivity on a hierarchical design with top level pipeline registers Oct 21, 2010 Issued
Array ( [id] => 5949363 [patent_doc_number] => 20110107285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Timing analysis apparatus, timing analysis method, and timing analysis program' [patent_app_type] => utility [patent_app_number] => 12/923887 [patent_app_country] => US [patent_app_date] => 2010-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7708 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107285.pdf [firstpage_image] =>[orig_patent_app_number] => 12923887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923887
Timing analysis apparatus, timing analysis method, and timing analysis program Oct 12, 2010 Issued
Array ( [id] => 8837313 [patent_doc_number] => 08453082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Soft error verification in hardware designs' [patent_app_type] => utility [patent_app_number] => 12/877117 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6617 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12877117 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877117
Soft error verification in hardware designs Sep 7, 2010 Issued
Array ( [id] => 8693327 [patent_doc_number] => 08392863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Method for circuit layout and rapid thermal annealing method for semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 12/877877 [patent_app_country] => US [patent_app_date] => 2010-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5143 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12877877 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/877877
Method for circuit layout and rapid thermal annealing method for semiconductor apparatus Sep 7, 2010 Issued
Array ( [id] => 7793147 [patent_doc_number] => 20120054703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'Virtual Flat Traversal Of A Hierarchical Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/868717 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11718 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054703.pdf [firstpage_image] =>[orig_patent_app_number] => 12868717 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868717
Virtual Flat Traversal Of A Hierarchical Circuit Design Aug 24, 2010 Abandoned
Menu