
Monjur Rahim
Examiner (ID: 13026, Phone: (571)270-3890 , Office: P/2436 )
| Most Active Art Unit | 2436 |
| Art Unit(s) | 2492, 2434, 2134, 2436 |
| Total Applications | 1026 |
| Issued Applications | 835 |
| Pending Applications | 72 |
| Abandoned Applications | 139 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9654560
[patent_doc_number] => 20140225565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'METHOD AND APPARATUS FOR PROVIDING ELECTRICAL ENERGY'
[patent_app_type] => utility
[patent_app_number] => 14/239590
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/239590 | Method and apparatus for providing electrical energy | Aug 18, 2011 | Issued |
Array
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[patent_doc_number] => 20120059499
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[patent_kind] => A1
[patent_issue_date] => 2012-03-08
[patent_title] => 'DESIGN AIDING DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM IN WHICH DESIGN AIDING PROGRAM IS STORED'
[patent_app_type] => utility
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Array
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[patent_title] => 'Method and apparatus for providing a layout defining a structure to be patterned onto a substrate'
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Array
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[patent_issue_date] => 2014-04-22
[patent_title] => 'Static analysis of VLSI reliability'
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Array
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[patent_issue_date] => 2016-01-19
[patent_title] => 'Method and apparatus for recharging a battery'
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Array
(
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[patent_title] => 'Mask data processing method for optimizing hierarchical structure'
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Array
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[patent_title] => 'METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/116557 | Method and apparatus for designing an integrated circuit | May 25, 2011 | Issued |
Array
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[id] => 8485269
[patent_doc_number] => 20120284676
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[patent_issue_date] => 2012-11-08
[patent_title] => 'DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS'
[patent_app_type] => utility
[patent_app_number] => 13/099767
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/099767 | Decoupling capacitor insertion using hypergraph connectivity analysis | May 2, 2011 | Issued |
Array
(
[id] => 9023646
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[patent_issue_date] => 2013-09-10
[patent_title] => 'Reducing narrow gate width effects in an integrated circuit design'
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Array
(
[id] => 10162054
[patent_doc_number] => 09193269
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[patent_issue_date] => 2015-11-24
[patent_title] => 'Vehicle charger mounting structure'
[patent_app_type] => utility
[patent_app_number] => 13/701248
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/701248 | Vehicle charger mounting structure | Apr 26, 2011 | Issued |
Array
(
[id] => 9214117
[patent_doc_number] => 20140013294
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[patent_kind] => A1
[patent_issue_date] => 2014-01-09
[patent_title] => 'METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN AND CORRESPONDING COMPUTER PROGRAM PRODUCT'
[patent_app_type] => utility
[patent_app_number] => 14/003361
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/003361 | Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product | Mar 27, 2011 | Issued |
Array
(
[id] => 8695195
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[patent_title] => 'SYSTEM AND METHOD FOR TRANSFERRING ELECTRIC ENERGY TO A VEHICLE'
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Array
(
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Array
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Array
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Array
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