Search

Monjur Rahim

Examiner (ID: 13026, Phone: (571)270-3890 , Office: P/2436 )

Most Active Art Unit
2436
Art Unit(s)
2492, 2434, 2134, 2436
Total Applications
1026
Issued Applications
835
Pending Applications
72
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7756702 [patent_doc_number] => 08112731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-07 [patent_title] => 'Congestion-driven placement systems and methods for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/277217 [patent_app_country] => US [patent_app_date] => 2008-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112731.pdf [firstpage_image] =>[orig_patent_app_number] => 12277217 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/277217
Congestion-driven placement systems and methods for programmable logic devices Nov 23, 2008 Issued
Array ( [id] => 8627057 [patent_doc_number] => 08359561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Equivalence verification between transaction level models and RTL at the example to processors' [patent_app_type] => utility [patent_app_number] => 12/275557 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 28744 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12275557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/275557
Equivalence verification between transaction level models and RTL at the example to processors Nov 20, 2008 Issued
Array ( [id] => 8235667 [patent_doc_number] => 08201127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-12 [patent_title] => 'Method and apparatus for reducing clock signal power consumption within an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/273407 [patent_app_country] => US [patent_app_date] => 2008-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201127.pdf [firstpage_image] =>[orig_patent_app_number] => 12273407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/273407
Method and apparatus for reducing clock signal power consumption within an integrated circuit Nov 17, 2008 Issued
Array ( [id] => 7683910 [patent_doc_number] => 20100122231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS' [patent_app_type] => utility [patent_app_number] => 12/269477 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122231.pdf [firstpage_image] =>[orig_patent_app_number] => 12269477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/269477
Electrically-driven optical proximity correction to compensate for non-optical effects Nov 11, 2008 Issued
Array ( [id] => 8472853 [patent_doc_number] => 08302046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Compact modeling of circuit stages for static timing analysis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/269037 [patent_app_country] => US [patent_app_date] => 2008-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 41 [patent_no_of_words] => 15741 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12269037 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/269037
Compact modeling of circuit stages for static timing analysis of integrated circuit designs Nov 10, 2008 Issued
Array ( [id] => 5266946 [patent_doc_number] => 20090119631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Variability-Aware Asynchronous Scheme for High-Performance Delay Matching' [patent_app_type] => utility [patent_app_number] => 12/265657 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 22583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119631.pdf [firstpage_image] =>[orig_patent_app_number] => 12265657 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265657
Variability-Aware Asynchronous Scheme for High-Performance Delay Matching Nov 4, 2008 Abandoned
Array ( [id] => 47955 [patent_doc_number] => 07784002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Systems for using relative positioning in structures with dynamic ranges' [patent_app_type] => utility [patent_app_number] => 12/253481 [patent_app_country] => US [patent_app_date] => 2008-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6988 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784002.pdf [firstpage_image] =>[orig_patent_app_number] => 12253481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/253481
Systems for using relative positioning in structures with dynamic ranges Oct 16, 2008 Issued
Array ( [id] => 5516915 [patent_doc_number] => 20090217222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/211842 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6038 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217222.pdf [firstpage_image] =>[orig_patent_app_number] => 12211842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/211842
SEMICONDUCTOR INTEGRATED CIRCUIT Sep 16, 2008 Abandoned
Array ( [id] => 6313174 [patent_doc_number] => 20100070942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'Automated Metal Pattern Generation for Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 12/210212 [patent_app_country] => US [patent_app_date] => 2008-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070942.pdf [firstpage_image] =>[orig_patent_app_number] => 12210212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/210212
Automated metal pattern generation for integrated circuits Sep 13, 2008 Issued
Array ( [id] => 5273751 [patent_doc_number] => 20090077527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'System for Determining Repetitive Work Units' [patent_app_type] => utility [patent_app_number] => 12/207962 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9981 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077527.pdf [firstpage_image] =>[orig_patent_app_number] => 12207962 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/207962
System for determining repetitive work units Sep 9, 2008 Issued
Array ( [id] => 5438022 [patent_doc_number] => 20090172609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'JITTER AMOUNT ESTIMATING METHOD, METHOD FOR CALCULATING CORRELATION BETWEEN AMOUNT OF SIMULTANEOUSLY OPERATING SIGNAL NOISE AND JITTER AMOUNT, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/201732 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10943 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172609.pdf [firstpage_image] =>[orig_patent_app_number] => 12201732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201732
Jitter amount estimating method, method for calculating correlation between amount of simultaneously operating signal noise and jitter amount, and recording medium Aug 28, 2008 Issued
Array ( [id] => 7495217 [patent_doc_number] => 08032854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => '3-stack floorplan for floating point unit' [patent_app_type] => utility [patent_app_number] => 12/201092 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3565 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032854.pdf [firstpage_image] =>[orig_patent_app_number] => 12201092 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201092
3-stack floorplan for floating point unit Aug 28, 2008 Issued
Array ( [id] => 4508910 [patent_doc_number] => 07958464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-07 [patent_title] => 'Electron beam patterning' [patent_app_type] => utility [patent_app_number] => 12/199922 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3534 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958464.pdf [firstpage_image] =>[orig_patent_app_number] => 12199922 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199922
Electron beam patterning Aug 27, 2008 Issued
Array ( [id] => 4626895 [patent_doc_number] => 08006207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Parallel intrusion search in hierarchical VLSI designs with substituting scan line' [patent_app_type] => utility [patent_app_number] => 12/198172 [patent_app_country] => US [patent_app_date] => 2008-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9795 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/006/08006207.pdf [firstpage_image] =>[orig_patent_app_number] => 12198172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/198172
Parallel intrusion search in hierarchical VLSI designs with substituting scan line Aug 25, 2008 Issued
Array ( [id] => 5273732 [patent_doc_number] => 20090077508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS' [patent_app_type] => utility [patent_app_number] => 12/193752 [patent_app_country] => US [patent_app_date] => 2008-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 17833 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077508.pdf [firstpage_image] =>[orig_patent_app_number] => 12193752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193752
ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS Aug 18, 2008 Abandoned
Array ( [id] => 8011117 [patent_doc_number] => 08086977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Design Structure for switching digital circuit clock net driver without losing clock pulses' [patent_app_type] => utility [patent_app_number] => 12/192272 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5545 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086977.pdf [firstpage_image] =>[orig_patent_app_number] => 12192272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/192272
Design Structure for switching digital circuit clock net driver without losing clock pulses Aug 14, 2008 Issued
Array ( [id] => 8343219 [patent_doc_number] => 08245161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-14 [patent_title] => 'Verification of computer simulation of photolithographic process' [patent_app_type] => utility [patent_app_number] => 12/190017 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5195 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12190017 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/190017
Verification of computer simulation of photolithographic process Aug 11, 2008 Issued
Array ( [id] => 7557513 [patent_doc_number] => 08069423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'System and method for model based multi-patterning optimization' [patent_app_type] => utility [patent_app_number] => 12/189692 [patent_app_country] => US [patent_app_date] => 2008-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 9781 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069423.pdf [firstpage_image] =>[orig_patent_app_number] => 12189692 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/189692
System and method for model based multi-patterning optimization Aug 10, 2008 Issued
Array ( [id] => 5523296 [patent_doc_number] => 20090031277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/177867 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12896 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031277.pdf [firstpage_image] =>[orig_patent_app_number] => 12177867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177867
Architectural physical synthesis Jul 21, 2008 Issued
Array ( [id] => 5523296 [patent_doc_number] => 20090031277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/177867 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12896 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031277.pdf [firstpage_image] =>[orig_patent_app_number] => 12177867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177867
Architectural physical synthesis Jul 21, 2008 Issued
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