
Monjur Rahim
Examiner (ID: 13026, Phone: (571)270-3890 , Office: P/2436 )
| Most Active Art Unit | 2436 |
| Art Unit(s) | 2492, 2434, 2134, 2436 |
| Total Applications | 1026 |
| Issued Applications | 835 |
| Pending Applications | 72 |
| Abandoned Applications | 139 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7756702
[patent_doc_number] => 08112731
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-02-07
[patent_title] => 'Congestion-driven placement systems and methods for programmable logic devices'
[patent_app_type] => utility
[patent_app_number] => 12/277217
[patent_app_country] => US
[patent_app_date] => 2008-11-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/08/112/08112731.pdf
[firstpage_image] =>[orig_patent_app_number] => 12277217
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/277217 | Congestion-driven placement systems and methods for programmable logic devices | Nov 23, 2008 | Issued |
Array
(
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[patent_doc_number] => 08359561
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[patent_kind] => B2
[patent_issue_date] => 2013-01-22
[patent_title] => 'Equivalence verification between transaction level models and RTL at the example to processors'
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[patent_app_date] => 2008-11-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/275557 | Equivalence verification between transaction level models and RTL at the example to processors | Nov 20, 2008 | Issued |
Array
(
[id] => 8235667
[patent_doc_number] => 08201127
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[patent_issue_date] => 2012-06-12
[patent_title] => 'Method and apparatus for reducing clock signal power consumption within an integrated circuit'
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[patent_app_date] => 2008-11-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/273407 | Method and apparatus for reducing clock signal power consumption within an integrated circuit | Nov 17, 2008 | Issued |
Array
(
[id] => 7683910
[patent_doc_number] => 20100122231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-13
[patent_title] => 'ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS'
[patent_app_type] => utility
[patent_app_number] => 12/269477
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/269477 | Electrically-driven optical proximity correction to compensate for non-optical effects | Nov 11, 2008 | Issued |
Array
(
[id] => 8472853
[patent_doc_number] => 08302046
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[patent_issue_date] => 2012-10-30
[patent_title] => 'Compact modeling of circuit stages for static timing analysis of integrated circuit designs'
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[patent_app_date] => 2008-11-11
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Array
(
[id] => 5266946
[patent_doc_number] => 20090119631
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[patent_title] => 'Variability-Aware Asynchronous Scheme for High-Performance Delay Matching'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/265657 | Variability-Aware Asynchronous Scheme for High-Performance Delay Matching | Nov 4, 2008 | Abandoned |
Array
(
[id] => 47955
[patent_doc_number] => 07784002
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[patent_title] => 'Systems for using relative positioning in structures with dynamic ranges'
[patent_app_type] => utility
[patent_app_number] => 12/253481
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[patent_app_date] => 2008-10-17
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[pdf_file] => patents/07/784/07784002.pdf
[firstpage_image] =>[orig_patent_app_number] => 12253481
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253481 | Systems for using relative positioning in structures with dynamic ranges | Oct 16, 2008 | Issued |
Array
(
[id] => 5516915
[patent_doc_number] => 20090217222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/211842
[patent_app_country] => US
[patent_app_date] => 2008-09-17
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12211842
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/211842 | SEMICONDUCTOR INTEGRATED CIRCUIT | Sep 16, 2008 | Abandoned |
Array
(
[id] => 6313174
[patent_doc_number] => 20100070942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-18
[patent_title] => 'Automated Metal Pattern Generation for Integrated Circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/210212 | Automated metal pattern generation for integrated circuits | Sep 13, 2008 | Issued |
Array
(
[id] => 5273751
[patent_doc_number] => 20090077527
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[patent_issue_date] => 2009-03-19
[patent_title] => 'System for Determining Repetitive Work Units'
[patent_app_type] => utility
[patent_app_number] => 12/207962
[patent_app_country] => US
[patent_app_date] => 2008-09-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/207962 | System for determining repetitive work units | Sep 9, 2008 | Issued |
Array
(
[id] => 5438022
[patent_doc_number] => 20090172609
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[patent_title] => 'JITTER AMOUNT ESTIMATING METHOD, METHOD FOR CALCULATING CORRELATION BETWEEN AMOUNT OF SIMULTANEOUSLY OPERATING SIGNAL NOISE AND JITTER AMOUNT, AND RECORDING MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 12/201732
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/201732 | Jitter amount estimating method, method for calculating correlation between amount of simultaneously operating signal noise and jitter amount, and recording medium | Aug 28, 2008 | Issued |
Array
(
[id] => 7495217
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[patent_title] => '3-stack floorplan for floating point unit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/201092 | 3-stack floorplan for floating point unit | Aug 28, 2008 | Issued |
Array
(
[id] => 4508910
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[patent_title] => 'Electron beam patterning'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/199922 | Electron beam patterning | Aug 27, 2008 | Issued |
Array
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[patent_title] => 'Parallel intrusion search in hierarchical VLSI designs with substituting scan line'
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Array
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Array
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Array
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Array
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