Search

Mudasiru K Olaegbe

Examiner (ID: 15599)

Most Active Art Unit
2495
Art Unit(s)
2495
Total Applications
95
Issued Applications
37
Pending Applications
49
Abandoned Applications
9

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8507128 [patent_doc_number] => 20120306535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/487859 [patent_app_country] => US [patent_app_date] => 2012-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11717 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13487859 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/487859
Sequential state elements in triple-mode redundant (TMR) state machines Jun 3, 2012 Issued
Array ( [id] => 8851462 [patent_doc_number] => 20130141137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'Stacked Physically Uncloneable Function Sense and Respond Module' [patent_app_type] => utility [patent_app_number] => 13/486500 [patent_app_country] => US [patent_app_date] => 2012-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5036 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13486500 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/486500
Stacked Physically Uncloneable Function Sense and Respond Module May 31, 2012 Abandoned
Array ( [id] => 8889106 [patent_doc_number] => 20130162290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'PARTIAL RECONFIGURATION CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 13/481506 [patent_app_country] => US [patent_app_date] => 2012-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8195 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13481506 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/481506
Partial reconfiguration circuitry May 24, 2012 Issued
Array ( [id] => 9497488 [patent_doc_number] => 08736309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Non-overlapping clock generator circuit and method' [patent_app_type] => utility [patent_app_number] => 13/479319 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479319 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/479319
Non-overlapping clock generator circuit and method May 23, 2012 Issued
Array ( [id] => 9032115 [patent_doc_number] => 20130234753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'Hysteresis-Based Latch Design for Improved Soft Error Rate with Low Area/Performance Overhead' [patent_app_type] => utility [patent_app_number] => 13/478760 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478760 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/478760
Hysteresis-based latch design for improved soft error rate with low area/performance overhead May 22, 2012 Issued
Array ( [id] => 9216887 [patent_doc_number] => 08629691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device' [patent_app_type] => utility [patent_app_number] => 13/474070 [patent_app_country] => US [patent_app_date] => 2012-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/474070
Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device May 16, 2012 Issued
Array ( [id] => 9145932 [patent_doc_number] => 20130300455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'MULTIPLE SIGNAL FORMAT OUTPUT DRIVER WITH CONFIGURABLE INTERNAL LOAD' [patent_app_type] => utility [patent_app_number] => 13/470055 [patent_app_country] => US [patent_app_date] => 2012-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5655 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13470055 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/470055
Multiple signal format output driver with configurable internal load May 10, 2012 Issued
Array ( [id] => 8493801 [patent_doc_number] => 20120293209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/467500 [patent_app_country] => US [patent_app_date] => 2012-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 24004 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13467500 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/467500
Logic circuit May 8, 2012 Issued
Array ( [id] => 8635280 [patent_doc_number] => 20130027084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'APPARATUS AND METHOD FOR DECODING AN ADDRESS IN TWO STAGES' [patent_app_type] => utility [patent_app_number] => 13/461322 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3517 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461322 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461322
Apparatus and method for decoding an address in two stages Apr 30, 2012 Issued
Array ( [id] => 8463000 [patent_doc_number] => 20120268168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'CLOCK GATING CELL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/450618 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4939 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450618 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450618
Clock gating cell circuit Apr 18, 2012 Issued
Array ( [id] => 9109811 [patent_doc_number] => 20130282943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'APPARATUS AND METHODS FOR A TAMPER RESISTANT BUS FOR SECURE LOCK BIT TRANSFER' [patent_app_type] => utility [patent_app_number] => 13/450765 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3693 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450765 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450765
Apparatus and methods for a tamper resistant bus for secure lock bit transfer Apr 18, 2012 Issued
Array ( [id] => 8564176 [patent_doc_number] => 20120326747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'RECONFIGURABLE LOGIC DEVICE' [patent_app_type] => utility [patent_app_number] => 13/449778 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5085 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449778 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449778
RECONFIGURABLE LOGIC DEVICE Apr 17, 2012 Abandoned
Array ( [id] => 9091790 [patent_doc_number] => 20130271101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'POWER CONVERSION SYSTEM EMPLOYING A TRI-STATE INTERFACE CIRCUIT AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 13/447730 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13447730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/447730
POWER CONVERSION SYSTEM EMPLOYING A TRI-STATE INTERFACE CIRCUIT AND METHOD OF OPERATION THEREOF Apr 15, 2012 Abandoned
Array ( [id] => 9350889 [patent_doc_number] => 08669784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-11 [patent_title] => 'Programmable pulse generator using inverter chain' [patent_app_type] => utility [patent_app_number] => 13/448176 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2691 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448176 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/448176
Programmable pulse generator using inverter chain Apr 15, 2012 Issued
Array ( [id] => 9246173 [patent_doc_number] => 08610458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Impedance control circuit and semiconductor device including the same' [patent_app_type] => utility [patent_app_number] => 13/446527 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 12955 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/446527
Impedance control circuit and semiconductor device including the same Apr 12, 2012 Issued
Array ( [id] => 8451257 [patent_doc_number] => 20120262202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'Output Buffer' [patent_app_type] => utility [patent_app_number] => 13/444870 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3304 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444870 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/444870
Output Buffer Apr 11, 2012 Abandoned
Array ( [id] => 9065551 [patent_doc_number] => 20130257307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'RELAMPING CIRCUIT FOR FLUORESCENT BALLASTS' [patent_app_type] => utility [patent_app_number] => 13/438034 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3849 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438034 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/438034
Relamping circuit for fluorescent ballasts Apr 2, 2012 Issued
Array ( [id] => 9553005 [patent_doc_number] => 08760059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Current-preheat electronic ballast and resonant capacitor adjusting circuit thereof' [patent_app_type] => utility [patent_app_number] => 13/437609 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437609 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437609
Current-preheat electronic ballast and resonant capacitor adjusting circuit thereof Apr 1, 2012 Issued
Array ( [id] => 8462861 [patent_doc_number] => 20120268029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'Circuit Arrangement and Method for Operating a Light Source, in Particular, a Light-Emitting Diode' [patent_app_type] => utility [patent_app_number] => 13/437749 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4917 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437749
Circuit arrangement and method for operating a light source, in particular, a light-emitting diode Apr 1, 2012 Issued
Array ( [id] => 9345728 [patent_doc_number] => 08664879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Circuit for driving fluorescent lamp and light-emitting diode' [patent_app_type] => utility [patent_app_number] => 13/437014 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3376 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437014 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437014
Circuit for driving fluorescent lamp and light-emitting diode Apr 1, 2012 Issued
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