Mudasiru K Olaegbe
Examiner (ID: 15599)
Most Active Art Unit | 2495 |
Art Unit(s) | 2495 |
Total Applications | 95 |
Issued Applications | 37 |
Pending Applications | 49 |
Abandoned Applications | 9 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 8507128
[patent_doc_number] => 20120306535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-06
[patent_title] => 'STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 13/487859
[patent_app_country] => US
[patent_app_date] => 2012-06-04
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/487859 | Sequential state elements in triple-mode redundant (TMR) state machines | Jun 3, 2012 | Issued |
Array
(
[id] => 8851462
[patent_doc_number] => 20130141137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-06
[patent_title] => 'Stacked Physically Uncloneable Function Sense and Respond Module'
[patent_app_type] => utility
[patent_app_number] => 13/486500
[patent_app_country] => US
[patent_app_date] => 2012-06-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/486500 | Stacked Physically Uncloneable Function Sense and Respond Module | May 31, 2012 | Abandoned |
Array
(
[id] => 8889106
[patent_doc_number] => 20130162290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-27
[patent_title] => 'PARTIAL RECONFIGURATION CIRCUITRY'
[patent_app_type] => utility
[patent_app_number] => 13/481506
[patent_app_country] => US
[patent_app_date] => 2012-05-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/481506 | Partial reconfiguration circuitry | May 24, 2012 | Issued |
Array
(
[id] => 9497488
[patent_doc_number] => 08736309
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-27
[patent_title] => 'Non-overlapping clock generator circuit and method'
[patent_app_type] => utility
[patent_app_number] => 13/479319
[patent_app_country] => US
[patent_app_date] => 2012-05-24
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/479319 | Non-overlapping clock generator circuit and method | May 23, 2012 | Issued |
Array
(
[id] => 9032115
[patent_doc_number] => 20130234753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-12
[patent_title] => 'Hysteresis-Based Latch Design for Improved Soft Error Rate with Low Area/Performance Overhead'
[patent_app_type] => utility
[patent_app_number] => 13/478760
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/478760 | Hysteresis-based latch design for improved soft error rate with low area/performance overhead | May 22, 2012 | Issued |
Array
(
[id] => 9216887
[patent_doc_number] => 08629691
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-14
[patent_title] => 'Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device'
[patent_app_type] => utility
[patent_app_number] => 13/474070
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/474070 | Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device | May 16, 2012 | Issued |
Array
(
[id] => 9145932
[patent_doc_number] => 20130300455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-14
[patent_title] => 'MULTIPLE SIGNAL FORMAT OUTPUT DRIVER WITH CONFIGURABLE INTERNAL LOAD'
[patent_app_type] => utility
[patent_app_number] => 13/470055
[patent_app_country] => US
[patent_app_date] => 2012-05-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/470055 | Multiple signal format output driver with configurable internal load | May 10, 2012 | Issued |
Array
(
[id] => 8493801
[patent_doc_number] => 20120293209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-22
[patent_title] => 'LOGIC CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/467500
[patent_app_country] => US
[patent_app_date] => 2012-05-09
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13467500
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/467500 | Logic circuit | May 8, 2012 | Issued |
Array
(
[id] => 8635280
[patent_doc_number] => 20130027084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-31
[patent_title] => 'APPARATUS AND METHOD FOR DECODING AN ADDRESS IN TWO STAGES'
[patent_app_type] => utility
[patent_app_number] => 13/461322
[patent_app_country] => US
[patent_app_date] => 2012-05-01
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461322
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/461322 | Apparatus and method for decoding an address in two stages | Apr 30, 2012 | Issued |
Array
(
[id] => 8463000
[patent_doc_number] => 20120268168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-25
[patent_title] => 'CLOCK GATING CELL CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/450618
[patent_app_country] => US
[patent_app_date] => 2012-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450618
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/450618 | Clock gating cell circuit | Apr 18, 2012 | Issued |
Array
(
[id] => 9109811
[patent_doc_number] => 20130282943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'APPARATUS AND METHODS FOR A TAMPER RESISTANT BUS FOR SECURE LOCK BIT TRANSFER'
[patent_app_type] => utility
[patent_app_number] => 13/450765
[patent_app_country] => US
[patent_app_date] => 2012-04-19
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450765
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/450765 | Apparatus and methods for a tamper resistant bus for secure lock bit transfer | Apr 18, 2012 | Issued |
Array
(
[id] => 8564176
[patent_doc_number] => 20120326747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-27
[patent_title] => 'RECONFIGURABLE LOGIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/449778
[patent_app_country] => US
[patent_app_date] => 2012-04-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/449778 | RECONFIGURABLE LOGIC DEVICE | Apr 17, 2012 | Abandoned |
Array
(
[id] => 9091790
[patent_doc_number] => 20130271101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-17
[patent_title] => 'POWER CONVERSION SYSTEM EMPLOYING A TRI-STATE INTERFACE CIRCUIT AND METHOD OF OPERATION THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/447730 | POWER CONVERSION SYSTEM EMPLOYING A TRI-STATE INTERFACE CIRCUIT AND METHOD OF OPERATION THEREOF | Apr 15, 2012 | Abandoned |
Array
(
[id] => 9350889
[patent_doc_number] => 08669784
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[patent_issue_date] => 2014-03-11
[patent_title] => 'Programmable pulse generator using inverter chain'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/448176 | Programmable pulse generator using inverter chain | Apr 15, 2012 | Issued |
Array
(
[id] => 9246173
[patent_doc_number] => 08610458
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-17
[patent_title] => 'Impedance control circuit and semiconductor device including the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/446527 | Impedance control circuit and semiconductor device including the same | Apr 12, 2012 | Issued |
Array
(
[id] => 8451257
[patent_doc_number] => 20120262202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-18
[patent_title] => 'Output Buffer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/444870 | Output Buffer | Apr 11, 2012 | Abandoned |
Array
(
[id] => 9065551
[patent_doc_number] => 20130257307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-03
[patent_title] => 'RELAMPING CIRCUIT FOR FLUORESCENT BALLASTS'
[patent_app_type] => utility
[patent_app_number] => 13/438034
[patent_app_country] => US
[patent_app_date] => 2012-04-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/438034 | Relamping circuit for fluorescent ballasts | Apr 2, 2012 | Issued |
Array
(
[id] => 9553005
[patent_doc_number] => 08760059
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Current-preheat electronic ballast and resonant capacitor adjusting circuit thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/437609 | Current-preheat electronic ballast and resonant capacitor adjusting circuit thereof | Apr 1, 2012 | Issued |
Array
(
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[patent_issue_date] => 2012-10-25
[patent_title] => 'Circuit Arrangement and Method for Operating a Light Source, in Particular, a Light-Emitting Diode'
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[patent_app_number] => 13/437749
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/437749 | Circuit arrangement and method for operating a light source, in particular, a light-emitting diode | Apr 1, 2012 | Issued |
Array
(
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[patent_title] => 'Circuit for driving fluorescent lamp and light-emitting diode'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/437014 | Circuit for driving fluorescent lamp and light-emitting diode | Apr 1, 2012 | Issued |